In the top_bit.v, the ASSP port mapping as an issue. The vector signals are mapped wronging in the top_bit.v,
The vector signals need to be mapped [msb:lsb] but its mapped [lsb:msb]:
Example: .WBs_WR_DAT({TILE_X1Y1_WBs_WR_DAT[0], .... TILE_X1Y1_WBs_WR_DAT[31]}),
But it should be mapped as:
.WBs_WR_DAT({TILE_X1Y1_WBs_WR_DAT[31], .... TILE_X1Y1_WBs_WR_DAT[0]}),

I have attached the top_bit.v file here.

design3_bit_v.zip