Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 119c6ad07d2e^
Choose a base ref
...
head repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 9895da82f7ae
Choose a head ref
  • 19 commits
  • 20 files changed
  • 1 contributor

Commits on May 19, 2020

  1. revC2: Bump revision. Remove ESD diode ground pads. 

    The main reason to remove the ground pads is assembly reliability. In
previous boards it was observed that it is fairly easy to create shorts
between the ground pads and signal pads of the package.
    @esden
    esden committed May 19, 2020

    Verified

    This commit was signed with the committer’s verified signature.
    lforst Luca Forstner
    SSH Key Fingerprint: ljpBJ7bYHpwPGV7Y7sJZM+cMS44wfy1fkQqwY/900Nw
    Verified
    Learn about vigilant mode
    Copy the full SHA
    119c6ad View commit details

  2. revC2: Changed SOT-563 footprint to improve assembly reliability. 

    The previous footprint was causing the solder stop webbing to be very
thin which can result in the webbing missing on PCBs and result in
shorts during reflow.
    @esden
    esden committed May 19, 2020
    Copy the full SHA
    68c8018 View commit details

  3. revC2: Updated the VREG DFN Footprints to match datasheet. 

    The datasheet has a finer footprint with smaller pads and smaller Via
drills.
    @esden
    esden committed May 19, 2020
    Copy the full SHA
    d1bdcff View commit details

  4. revC2: Updated a bunch of the footprints to the upstream versions. 

    This change seems like a big diff but it only really changes SOIC-8 and
MSOP-8. They mostly bring roundrect changes and increase pad length for
better fileting.
    @esden
    esden committed May 19, 2020
    Copy the full SHA
    e6e06c3 View commit details

  5. revC2: Replaced rpack8->4 and level shifter package. 

    * The 8x resistor arrays are not as common as 4x. Thus the 8x end up being
more expensive and harder to source.
* The SOT-563 package has slightly harder to solder than the SOT-363.
Also the level shifter in SOT-363 is lower cost.
    @esden
    esden committed May 19, 2020
    Copy the full SHA
    4ea2268 View commit details

  6. revC2: Updated TSSOP footprint to get roundrect pads.

    @esden
    esden committed May 19, 2020
    Copy the full SHA
    881afe0 View commit details

  7. revC2: Updated UDFN-18 to roundrect pads.

    @esden
    esden committed May 19, 2020
    Copy the full SHA
    662a8aa View commit details

  8. revC2: All swapped all remaining missing roundrect footprints. 

    All footprints that are still not roundrect in the official KiCad
library moved to local Glasgow footprint library and updated to
roundrect pads.

Also made a version of the 2x22 pin 1.27mm pitch LVDS connector with
alignment pins. This will allow us to have accurate enough position of
the connector so we can reliably connect to it in the pogopin tester and
to possible daugter boards.
    @esden
    esden committed May 19, 2020
    Copy the full SHA
    7cfdd41 View commit details

Commits on May 20, 2020

  1. revC2: Initial routing pass after changing out parts.

    @esden
    esden committed May 20, 2020
    Copy the full SHA
    14b01d8 View commit details

Commits on May 22, 2020

  1. revC2: Spread level shifters to respect courtyards. 

    As part of rerouting also moved half of the power via under the
packages. We regained some space thanks to that resulting in slightly
cleaner routing.
    @esden
    esden committed May 22, 2020
    Copy the full SHA
    3ff3b82 View commit details

Commits on May 23, 2020

  1. revC2: Part ID removed from silkscreen, added logic block legends. 

    All part IDs and values are now meant to be printed on the Fab layer as
hardcopy manual assembly and population guide. The space on the
silkscreen used for part IDs was partly traded against logical circuit
block documentation. This is just the first pass and meant as a stepping
stone. The goal is to have the logical functionality be as self
descriptive on the silkscreen as possible.
    @esden
    esden committed May 23, 2020
    Copy the full SHA
    a5f364b View commit details

Commits on May 26, 2020

  1. revC2: Some minor silkscreen legend improvements. 

    Mainly improved readability of the Pull-Up/-Down control block legend.
This resulted in some of the passives being moved out of the way to make
space for the legend. Also added legend that indicates which level
shifter is responsible for which IO signal, including Sync.
    @esden
    esden committed May 26, 2020
    Copy the full SHA
    409c714 View commit details

  2. revC2: Align inline resistors and Sync level shifter. 

    They were not aligned in a vertical line. For aethetic reasons this is
now fixed. :)
    @esden
    esden committed May 26, 2020
    Copy the full SHA
    8574b92 View commit details

  3. revC2: Replaced HiZ with P- to better reflect the actual function. 

    The GPIO extenders can set a Pull-Up/-Down resistor or do nothing. That
is not the same thing as HiZ. HiZ is only true if the level shifters are
also set to input. So P- (Pull nothing or Passive) is a better term.
    @esden
    esden committed May 26, 2020
    Copy the full SHA
    fcfe73c View commit details

Commits on Jun 2, 2020

  1. revC2: Swapped Micro USB for USB-C USB 2.0 connector. 

    This is the inital routing pass. This is the status after esden's Twitch
stream on Tuesday May 26th 2020.
    @esden
    esden committed Jun 2, 2020
    Copy the full SHA
    a09743a View commit details

  2. revC2: Rerouted and cleaned the USB current limit switch section.

    @esden
    esden committed Jun 2, 2020
    Copy the full SHA
    7ea3ce0 View commit details

  3. revC2: Added Mfr name and logo anchors.

    @esden
    esden committed Jun 2, 2020
    Copy the full SHA
    3b16bea View commit details

Commits on Jun 5, 2020

  1. revC2: Added top silk bank pin legend.

    @esden
    esden committed Jun 5, 2020
    Copy the full SHA
    46a75c4 View commit details

  2. revC2: Made back side silkscreen black on white compatible. 

    Replaced nono_hana with an outlive version and made the Serial Number
box an outline. This will make the black silkscreen on white solder mask
look "right". Should still work for light silk on dark solder stop.
    @esden
    esden committed Jun 5, 2020
    Copy the full SHA
    9895da8 View commit details
140 changes: 72 additions & 68 deletions hardware/boards/glasgow/glasgow-cache.lib
View file
Original file line number Diff line number Diff line change
@@ -293,39 +293,61 @@ X 1 1 0 0 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_USB_B_Micro
#
DEF Connector_USB_B_Micro J 0 40 Y Y 1 F N
F0 "J" -200 450 50 H V L CNN
F1 "Connector_USB_B_Micro" -200 350 50 H V L CNN
F2 "" 150 -50 50 H I C CNN
F3 "" 150 -50 50 H I C CNN
ALIAS USB_B_Mini
# Connector_USB_C_Receptacle_USB2.0
#
DEF Connector_USB_C_Receptacle_USB2.0 J 0 40 Y Y 1 F N
F0 "J" -400 750 50 H V L CNN
F1 "Connector_USB_C_Receptacle_USB2.0" 750 750 50 H V R CNN
F2 "" 150 0 50 H I C CNN
F3 "" 150 0 50 H I C CNN
$FPLIST
USB*
USB*C*Receptacle*
$ENDFPLIST
DRAW
C -150 85 25 0 1 10 F
C -25 135 15 0 1 10 F
S -200 -300 200 300 0 1 10 f
S -5 -300 5 -270 0 1 0 N
S 10 50 -20 20 0 1 10 F
S 200 -205 170 -195 0 1 0 N
S 200 -105 170 -95 0 1 0 N
S 200 -5 170 5 0 1 0 N
S 200 195 170 205 0 1 0 N
P 2 0 1 10 -75 85 25 85 N
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
P 4 0 1 10 25 110 25 60 75 85 25 110 F
P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
X VBUS 1 300 200 100 L 50 50 1 1 w
X D- 2 300 -100 100 L 50 50 1 1 P
X D+ 3 300 0 100 L 50 50 1 1 P
X ID 4 300 -200 100 L 50 50 1 1 P
X GND 5 0 -400 100 U 50 50 1 1 w
X Shield 6 -100 -400 100 U 50 50 1 1 P
A -275 -150 75 -1799 -1 0 1 20 N -350 -150 -200 -150
A -275 -150 25 -1799 -1 0 1 10 N -300 -150 -250 -150
A -275 -150 25 -1799 -1 0 1 10 F -300 -150 -250 -150
A -275 150 25 1 1799 0 1 10 F -250 150 -300 150
A -275 150 25 1 1799 0 1 10 N -250 150 -300 150
A -275 150 75 1 1799 0 1 20 N -200 150 -350 150
C -100 45 25 0 1 10 F
C 0 -230 50 0 1 0 F
S -10 -700 10 -660 0 0 0 N
S 400 -590 360 -610 0 0 0 N
S 400 -490 360 -510 0 0 0 N
S 400 -190 360 -210 0 0 0 N
S 400 -90 360 -110 0 0 0 N
S 400 10 360 -10 0 0 0 N
S 400 110 360 90 0 0 0 N
S 400 310 360 290 0 0 0 N
S 400 410 360 390 0 0 0 N
S 400 610 360 590 0 0 0 N
S -400 700 400 -700 0 1 10 f
S -300 -150 -250 150 0 1 10 F
S 75 70 125 120 0 1 10 F
P 2 0 1 20 -350 -150 -350 150 N
P 2 0 1 20 -200 150 -200 -150 N
P 2 0 1 20 0 -230 0 170 N
P 3 0 1 20 0 -130 -100 -30 -100 20 N
P 3 0 1 20 0 -80 100 20 100 70 N
P 4 0 1 10 -50 170 0 270 50 170 -50 170 F
X GND A1 0 -900 200 U 50 50 1 1 W
X GND A12 0 -900 200 U 50 50 1 1 P N
X VBUS A4 600 600 200 L 50 50 1 1 W
X CC1 A5 600 400 200 L 50 50 1 1 B
X D+ A6 600 -100 200 L 50 50 1 1 B
X D- A7 600 100 200 L 50 50 1 1 B
X SBU1 A8 600 -500 200 L 50 50 1 1 B
X VBUS A9 600 600 200 L 50 50 1 1 P N
X GND B1 0 -900 200 U 50 50 1 1 P N
X GND B12 0 -900 200 U 50 50 1 1 P N
X VBUS B4 600 600 200 L 50 50 1 1 P N
X CC2 B5 600 300 200 L 50 50 1 1 B
X D+ B6 600 -200 200 L 50 50 1 1 B
X D- B7 600 0 200 L 50 50 1 1 B
X SBU2 B8 600 -600 200 L 50 50 1 1 B
X VBUS B9 600 600 200 L 50 50 1 1 P N
X SHIELD S1 -300 -900 200 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
@@ -409,8 +431,8 @@ $FPLIST
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 3 0 1 8 -50 -50 -50 50 -30 50 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 3 0 1 10 -50 -50 -50 50 -30 50 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
@@ -450,9 +472,9 @@ $FPLIST
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
@@ -477,31 +499,25 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Pack08
# Device_R_Pack04
#
DEF Device_R_Pack08 RN 0 0 Y N 1 F N
F0 "RN" -500 0 50 V V C CNN
F1 "Device_R_Pack08" 400 0 50 V V C CNN
F2 "" 475 0 50 V I C CNN
DEF Device_R_Pack04 RN 0 0 Y N 1 F N
F0 "RN" -300 0 50 V V C CNN
F1 "Device_R_Pack04" 200 0 50 V V C CNN
F2 "" 275 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*
SOIC*
R*Array*Concave*
R*Array*Convex*
$ENDFPLIST
DRAW
S -450 -95 350 95 0 1 10 f
S -425 75 -375 -75 0 1 10 N
S -325 75 -275 -75 0 1 10 N
S -250 -95 150 95 0 1 10 f
S -225 75 -175 -75 0 1 10 N
S -125 75 -75 -75 0 1 10 N
S -25 75 25 -75 0 1 10 N
S 75 75 125 -75 0 1 10 N
S 175 75 225 -75 0 1 10 N
S 275 75 325 -75 0 1 10 N
P 2 0 1 0 -400 -100 -400 -75 N
P 2 0 1 0 -400 75 -400 100 N
P 2 0 1 0 -300 -100 -300 -75 N
P 2 0 1 0 -300 75 -300 100 N
P 2 0 1 0 -200 -100 -200 -75 N
P 2 0 1 0 -200 75 -200 100 N
P 2 0 1 0 -100 -100 -100 -75 N
@@ -510,26 +526,14 @@ P 2 0 1 0 0 -100 0 -75 N
P 2 0 1 0 0 75 0 100 N
P 2 0 1 0 100 -100 100 -75 N
P 2 0 1 0 100 75 100 100 N
P 2 0 1 0 200 -100 200 -75 N
P 2 0 1 0 200 75 200 100 N
P 2 0 1 0 300 -100 300 -75 N
P 2 0 1 0 300 75 300 100 N
X R1.1 1 -400 -200 100 U 50 50 1 1 P
X R7.2 10 200 200 100 D 50 50 1 1 P
X R6.2 11 100 200 100 D 50 50 1 1 P
X R5.2 12 0 200 100 D 50 50 1 1 P
X R4.2 13 -100 200 100 D 50 50 1 1 P
X R3.2 14 -200 200 100 D 50 50 1 1 P
X R2.2 15 -300 200 100 D 50 50 1 1 P
X R1.2 16 -400 200 100 D 50 50 1 1 P
X R2.1 2 -300 -200 100 U 50 50 1 1 P
X R3.1 3 -200 -200 100 U 50 50 1 1 P
X R4.1 4 -100 -200 100 U 50 50 1 1 P
X R5.1 5 0 -200 100 U 50 50 1 1 P
X R6.1 6 100 -200 100 U 50 50 1 1 P
X R7.1 7 200 -200 100 U 50 50 1 1 P
X R8.1 8 300 -200 100 U 50 50 1 1 P
X R8.2 9 300 200 100 D 50 50 1 1 P
X R1.1 1 -200 -200 100 U 50 50 1 1 P
X R2.1 2 -100 -200 100 U 50 50 1 1 P
X R3.1 3 0 -200 100 U 50 50 1 1 P
X R4.1 4 100 -200 100 U 50 50 1 1 P
X R4.2 5 100 200 100 D 50 50 1 1 P
X R3.2 6 0 200 100 D 50 50 1 1 P
X R2.2 7 -100 200 100 D 50 50 1 1 P
X R1.2 8 -200 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
Loading