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fromnmigenimport*fromnmigen.buildimport*fromnmigen_boardsimportversa_ecp5_5gasFPGAclassTest(Elaboratable):
defelaborate(self, platform):
broken=Trueifbroken:
platform.add_resources([Resource("test", 0, Pins("A6"))])
else:
platform.add_resources([Resource("test", 0, Pins("A6", dir="o"))])
pin=platform.request("test")
m=Module()
m.submodules+=Instance("OSCG", o_OSC=pin) # It is important that this is an outputreturnmif__name__=="__main__":
FPGA.VersaECP55GPlatform().build(Test())
fails with
python mcve-assert-defs.py 1 ✘ 21:04:46
Traceback (most recent call last):
File "mcve-assert-defs.py", line 20, in <module>
FPGA.VersaECP55GPlatform().build(Test())
File "/home/user/.local/lib/python3.8/site-packages/nmigen/build/plat.py", line 90, in build
plan = self.prepare(elaboratable, name, **kwargs)
File "/home/user/.local/lib/python3.8/site-packages/nmigen/build/plat.py", line 162, in prepare
fragment._propagate_ports(ports=self.iter_ports(), all_undef_as_ports=False)
File "/home/user/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py", line 462, in _propagate_ports
self._prepare_use_def_graph(parent, level, uses, defs, ios, self)
File "/home/user/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py", line 436, in _prepare_use_def_graph
subfrag._prepare_use_def_graph(parent, level, uses, defs, ios, top)
File "/home/user/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py", line 428, in _prepare_use_def_graph
add_defs(value._lhs_signals())
File "/home/user/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py", line 396, in add_defs
assert defs[sig] is self
AssertionError
setting broken to 'False' makes it compile just fine.
Similar issues are in #320 and #191
The text was updated successfully, but these errors were encountered:
Executing
fails with
setting broken to 'False' makes it compile just fine.
Similar issues are in #320 and #191
The text was updated successfully, but these errors were encountered: