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base repository: azonenberg/starshipraider
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  • 2 commits
  • 11 files changed
  • 1 contributor

Commits on May 1, 2020

  1. Initial version of sma-test board

    @azonenberg
    azonenberg committed May 1, 2020
    Copy the full SHA
    1fdf3aa View commit details

  2. Added more simulations

    @azonenberg
    azonenberg committed May 1, 2020
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    40fd0b5 View commit details
2 changes: 2 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/.gitignore
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output
*bak
2,150 changes: 2,150 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/fp-info-cache
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29 changes: 29 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/sma-test-cache.lib
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Conn_Coaxial
#
DEF Connector_Conn_Coaxial J 0 40 Y N 1 F N
F0 "J" 10 120 50 H V C CNN
F1 "Connector_Conn_Coaxial" 115 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*BNC*
*SMA*
*SMB*
*SMC*
*Cinch*
$ENDFPLIST
DRAW
A -2 0 71 1636 0 0 1 10 N -70 20 70 0
A -1 0 71 0 -1638 0 1 10 N 70 0 -70 -20
C 0 0 20 0 1 8 N
P 2 0 1 0 -50 0 -20 0 N
P 2 0 1 0 0 -100 0 -70 N
X In 1 -150 0 100 R 50 50 1 1 P
X Ext 2 0 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library
375 changes: 375 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/sma-test.kicad_pcb
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241 changes: 241 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/sma-test.pro
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update=Fri 01 May 2020 05:28:30 AM PDT
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.125
MinViaDiameter=0.5499999999999999
MinViaDrill=0.25
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.41
TrackWidth2=0.41
ViaDiameter1=0.55
ViaDrill1=0.25
ViaDiameter2=0.55
ViaDrill2=0.25
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0.05
SolderPasteClearance=0
SolderPasteRatio=-0.05
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=3
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.125
TrackWidth=0.41
ViaDiameter=0.55
ViaDrill=0.25
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
46 changes: 46 additions & 0 deletions boards/probes/oshpark-sma-test/sma-test/sma-test.sch
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector:Conn_Coaxial J2
U 1 1 5EAC10CB
P 4600 2500
F 0 "J2" H 4700 2475 50 0000 L CNN
F 1 "Conn_Coaxial" H 4700 2384 50 0000 L CNN
F 2 "azonenberg_pcb:CONN_SMA_EDGE_AMPHENOL_901_10511_3" H 4600 2500 50 0001 C CNN
F 3 "" H 4600 2500 50 0001 C CNN
1 4600 2500
1 0 0 -1
$EndComp
$Comp
L Connector:Conn_Coaxial J1
U 1 1 5EAC16CE
P 3750 2500
F 0 "J1" H 3703 2738 50 0000 C CNN
F 1 "Conn_Coaxial" H 3703 2647 50 0000 C CNN
F 2 "azonenberg_pcb:CONN_SMA_EDGE_AMPHENOL_901_10511_3" H 3750 2500 50 0001 C CNN
F 3 "" H 3750 2500 50 0001 C CNN
1 3750 2500
-1 0 0 -1
$EndComp
Wire Wire Line
3900 2500 4450 2500
Wire Wire Line
4600 2700 3750 2700
Text Label 4050 2700 0 50 ~ 0
GND
Text Label 4050 2500 0 50 ~ 0
SIGNAL
$EndSCHEMATC
151 changes: 151 additions & 0 deletions sims/handheld-resistive-probe/cpw-short-segment-nores.son
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FTYP SONPROJ 17 ! Sonnet Project File
VER 17.52.2
HEADER
LIC antikernel2.1.48685 90e2ba8817c0 havequick azonenberg
DAT 04/27/2020 08:39:31
BUILT_BY_CREATED xgeom 16.56 07/03/2018 15:05:41
BUILT_BY_SAVED sonnet 17.52.2
MDATE 04/27/2020 08:39:31
HDATE 04/27/2020 08:39:31
ANN _gk:
ANN
ANN disabled symmetry
ANN dleted lower air layer and internal groundplane
ANN using analysis box bottom cover as groundplane
ANN assigned the via rectangles to the Via1 tech layer
ANN stretched the via ends to connect with the east and west boxwalls
ANN made via rectangles symmetrical about Y
ANN defined new Copper_Gnd normal metal type
ANN changed box bottom cover from freespace to Copper_Gnd
ANN
ANN _gk2:
ANN
ANN per Matt crash is caused by incorrect port handling with symmetry, component below the line of symmetry, and ABS.
ANN most efficient workaround is to delete the resistor components below the line of symmetry
ANN then symmetry can still be used
ANN this is what i did in this model
ANN
ANN
ANN
END HEADER
DIM
ANG DEG
CAP PF
CON /OH
FREQ GHZ
IND NH
LNG MM
RES OH
END DIM
CONTROL
VARSWP
OPTIONS -dj
SPEED 0
CACHE_ABS 1
Q_ACC N
END CONTROL
GEO
SYM
TMET "Free Space" 0 FREESPACE 376.7303136 0 0 0
BMET "Copper_Gnd" 2 NOR 58000000 0 0.035
MET "Copper" 1 TMM 58000000 0.5 0.035 3
BOX 2 1.5 5 120 400 20 0
1 1 1 0 0 0 0 "Air"
0.508 3.66 1 0.0037 0 0 0 "Rogers RO4350B"
1 1 1 0 0 0 0 "Air"
TECHLAY METAL Metal1 <UNSPECIFIED> -2 0
0 0 0 N 0 1 1 100 100 0 0 0 Y
END
END
TECHLAY VIA Via1 <UNSPECIFIED> -4 0
VIA POLYGON
0 0 -1 N 0 1 1 100 100 0 0 0 Y
TOLEVEL 1 RING NOCOVERS
END
END
TECHLAY METAL Metal2 <UNSPECIFIED> -3 0
1 0 -1 N 0 1 1 100 100 0 0 0 Y
END
END
LORGN 0 250 U
POR1 BOX
POLY 12 1
1
1 50 0 0 0 1.5 2.5
POR1 BOX
POLY 16 1
3
2 50 0 0 0 0 2.5
NUM 7
0 5 0 N 10 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 0
1.5 0
1.5 2.15
0 2.15
0 0
END
0 5 0 N 11 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 2.85
1.5 2.85
1.5 5
0 5
0 2.85
END
0 5 0 N 12 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
1 2.25
1.5 2.25
1.5 2.75
1 2.75
1 2.25
END
0 5 0 N 16 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 2.25
0.5 2.25
0.5 2.75
0 2.75
0 2.25
END
VIA POLYGON
0 5 -1 N 21 1 1 100 100 0 0 0 Y
TOLEVEL 1 RING NOCOVERS
TLAYNAM Via1 INH
0 2.9875
1.5 2.9875
1.5 4.0875
0 4.0875
0 2.9875
END
VIA POLYGON
0 5 -1 N 22 1 1 100 100 0 0 0 Y
TOLEVEL 1 RING NOCOVERS
TLAYNAM Via1 INH
0 0.8875
1.5 0.8875
1.5 1.9875
0 1.9875
0 0.8875
END
1 5 -1 N 25 1 1 100 100 0 0 0 Y
TLAYNAM Metal2 INH
0 0
1.5 0
1.5 5
0 5
0 0
END
END GEO
OPT
MAX 100
END OPT
VARSWP
ENABLED Y
FREQ Y AY ABS_ENTRY 0.1 10.0 -1 300
END
END VARSWP
FILEOUT
FOLDER .
END FILEOUT
2 changes: 2 additions & 0 deletions sims/oshpark-sma-test/.gitignore
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*bck
sondata
568 changes: 568 additions & 0 deletions sims/oshpark-sma-test/oshpark-sma-test.son
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182 changes: 182 additions & 0 deletions sims/probe-characterization/cpw-section-0402.son
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FTYP SONPROJ 17 ! Sonnet Project File
VER 17.52.2
HEADER
LIC antikernel2.1.48685 90e2ba8817c0 havequick azonenberg
DAT 04/27/2020 08:38:28
BUILT_BY_CREATED xgeom 16.56 07/03/2018 15:05:41
BUILT_BY_SAVED sonnet 17.52.2
MDATE 04/27/2020 08:38:28
HDATE 04/27/2020 08:38:28
END HEADER
DIM
ANG DEG
CAP PF
CON /OH
FREQ GHZ
IND NH
LNG MM
RES OH
END DIM
CONTROL
VARSWP
OPTIONS -dj
SPEED 0
CACHE_ABS 1
Q_ACC N
END CONTROL
GEO
SYM
TMET "Free Space" 0 FREESPACE 376.7303136 0 0 0
BMET "Free Space" 0 FREESPACE 376.7303136 0 0 0
MET "Silver" 1 TMM 61700000 0.5 0.035 3
BOX 2 10 5 160 400 20 0
1 1 1 0 0 0 0 "Air"
1.5 3.5 1 0.0037 0 0 0 "Rogers RO4350B"
1 1 1 0 0 0 0 "Substrate"
TECHLAY METAL Metal1 <UNSPECIFIED> -2 0
0 0 0 N 0 1 1 100 100 0 0 0 Y
END
END
TECHLAY METAL Metal2 <UNSPECIFIED> -3 0
1 0 -1 N 0 1 1 100 100 0 0 0 Y
END
END
VALVAR WIDTH LNG 0.8 "Dim. Param."
GEOVAR WIDTH SYM YDIR 1 NSCD
POS -0.3883799166 0.1211317413
NOM 0.8
REF1 POLY 10 1
0
REF2 POLY 10 1
3
PS1 1
POLY 10 1
1
END
PS2 1
POLY 10 1
2
END
END
VALVAR TOPSPACE LNG 0.1 "Dim. Param."
GEOVAR TOPSPACE ANC YDIR -1 NSCD
POS -0.5684970549 -0.07160206473
NOM 0.1
REF1 POLY 10 1
0
REF2 POLY 13 1
3
PS1 0
END
PS2 1
POLY 13 1
2
END
END
VALVAR BOTSPACE LNG 0.1 "Dim. Param."
GEOVAR BOTSPACE ANC YDIR 1 NSCD
POS -0.4042321581 -0.2386413607
NOM 0.1
REF1 POLY 10 1
3
REF2 POLY 14 1
0
PS1 0
END
PS2 1
POLY 14 1
1
END
END
DIM STD XDIR 1
POS 0.6544601443 0.02429647291
NOM 0.5
REF1 POLY 10 1
1
REF2 POLY 31 1
0
END
LORGN 0 250 U
POR1 BOX
POLY 10 1
3
1 50 0 0 0 0 2.5
POR1 BOX
POLY 31 1
1
2 50 0 0 0 10 2.5
NUM 7
0 5 0 N 10 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 2.1
4.75 2.1
4.75 2.9
0 2.9
0 2.1
END
0 5 0 N 13 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 0
10 0
10 2
0 2
0 0
END
0 5 0 N 14 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
0 3
10 3
10 5
0 5
0 3
END
0 5 0 N 31 1 1 100 100 0 0 0 Y
TLAYNAM Metal1 INH
5.25 2.1
10 2.1
10 2.9
5.25 2.9
5.25 2.1
END
VIA POLYGON
0 5 -1 N 15 1 1 100 100 0 0 0 Y
TOLEVEL 1 RING NOCOVERS
0 0.65
10 0.65
10 1.65
0 1.65
0 0.65
END
VIA POLYGON
0 5 -1 N 16 1 1 100 100 0 0 0 Y
TOLEVEL 1 RING NOCOVERS
0 3.35
10 3.35
10 4.4
0 4.4
0 3.35
END
1 5 -1 N 19 1 1 100 100 0 0 0 Y
TLAYNAM Metal2 INH
0 0
10 0
10 5
0 5
0 0
END
END GEO
OPT
MAX 100
END OPT
VARSWP
SWPVARS ON
ENABLED Y
FREQ Y AY ABS_ENTRY 0.1 10.0 -1 300
VAR WIDTH Y 0.725 0.875 0.025
VAR TOPSPACE N 0.1 0.1 UNDEF
VAR BOTSPACE N 0.1 0.1 UNDEF
END
END VARSWP
FILEOUT
FOLDER .
END FILEOUT
644 changes: 644 additions & 0 deletions sims/probe-characterization/sma-couple.son
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