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compare: 567aab54123e
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Jun 21, 2020

  1. Added ferrites to 12V power outputs to improve EMC performance. Fixed… 

    … incorrect 1V0 hookup for small FPGA. Fixed some other ERC errors
    @azonenberg
    azonenberg committed Jun 21, 2020
    Copy the full SHA
    567aab5 View commit details
362 changes: 235 additions & 127 deletions boards/MAXWELL/maxwell-main/inputs.sch
View file
Original file line number Diff line number Diff line change
@@ -14,39 +14,39 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 3200 1300 1350 1950
S 3050 1300 1350 1950
U 5F0BA462
F0 "Pod Power" 50
F1 "podpower.sch" 50
F2 "3V3" I L 3200 1450 50
F3 "12V0" I L 3200 1350 50
F4 "GND" I L 3200 1550 50
F5 "P0_12V0" O L 3200 1750 50
F6 "P0_PRESENT" I L 3200 1850 50
F7 "P1_PRESENT" I L 3200 2050 50
F8 "P2_PRESENT" I L 3200 2250 50
F9 "P3_PRESENT" I L 3200 2450 50
F10 "P4_PRESENT" I L 3200 2650 50
F11 "P5_PRESENT" I L 3200 2850 50
F12 "P6_PRESENT" I R 4550 1850 50
F13 "P7_PRESENT" I R 4550 2050 50
F14 "P8_PRESENT" I R 4550 2250 50
F15 "P9_PRESENT" I R 4550 2450 50
F16 "P10_PRESENT" I R 4550 2650 50
F17 "P11_PRESENT" I R 4550 2850 50
F18 "P1_12V0" O L 3200 1950 50
F19 "P2_12V0" O L 3200 2150 50
F20 "P3_12V0" O L 3200 2350 50
F21 "P4_12V0" O L 3200 2550 50
F22 "P5_12V0" O L 3200 2750 50
F23 "P6_12V0" O R 4550 1750 50
F24 "P7_12V0" O R 4550 1950 50
F25 "P8_12V0" O R 4550 2150 50
F26 "P9_12V0" O R 4550 2350 50
F27 "P10_12V0" O R 4550 2550 50
F28 "P11_12V0" O R 4550 2750 50
F29 "I2C_SDA" B L 3200 3050 50
F30 "I2C_SCL" I L 3200 3150 50
F2 "3V3" I L 3050 1450 50
F3 "12V0" I L 3050 1350 50
F4 "GND" I L 3050 1550 50
F5 "P0_12V0" O L 3050 1750 50
F6 "P0_PRESENT" I L 3050 1850 50
F7 "P1_PRESENT" I L 3050 2050 50
F8 "P2_PRESENT" I L 3050 2250 50
F9 "P3_PRESENT" I L 3050 2450 50
F10 "P4_PRESENT" I L 3050 2650 50
F11 "P5_PRESENT" I L 3050 2850 50
F12 "P6_PRESENT" I R 4400 1850 50
F13 "P7_PRESENT" I R 4400 2050 50
F14 "P8_PRESENT" I R 4400 2250 50
F15 "P9_PRESENT" I R 4400 2450 50
F16 "P10_PRESENT" I R 4400 2650 50
F17 "P11_PRESENT" I R 4400 2850 50
F18 "P1_12V0" O L 3050 1950 50
F19 "P2_12V0" O L 3050 2150 50
F20 "P3_12V0" O L 3050 2350 50
F21 "P4_12V0" O L 3050 2550 50
F22 "P5_12V0" O L 3050 2750 50
F23 "P6_12V0" O R 4400 1750 50
F24 "P7_12V0" O R 4400 1950 50
F25 "P8_12V0" O R 4400 2150 50
F26 "P9_12V0" O R 4400 2350 50
F27 "P10_12V0" O R 4400 2550 50
F28 "P11_12V0" O R 4400 2750 50
F29 "I2C_SDA" B L 3050 3050 50
F30 "I2C_SCL" I L 3050 3150 50
$EndSheet
$Comp
L xilinx-azonenberg:XC7Sx-FTGB196 U?
@@ -199,30 +199,6 @@ Text Label 9100 4250 2 50 ~ 0
P11_UART_TX
Text Label 9100 4350 2 50 ~ 0
P11_UART_RX
Wire Wire Line
4550 1750 5000 1750
Wire Wire Line
5000 1850 4550 1850
Wire Wire Line
4550 1950 5000 1950
Wire Wire Line
5000 2050 4550 2050
Wire Wire Line
4550 2150 5000 2150
Wire Wire Line
5000 2250 4550 2250
Wire Wire Line
4550 2350 5000 2350
Wire Wire Line
5000 2450 4550 2450
Wire Wire Line
4550 2550 5000 2550
Wire Wire Line
5000 2650 4550 2650
Wire Wire Line
4550 2750 5000 2750
Wire Wire Line
5000 2850 4550 2850
Text HLabel 6600 3050 2 50 Input ~ 0
K7_CLK_P
Text HLabel 6600 3150 2 50 Input ~ 0
@@ -301,26 +277,26 @@ Text Label 6350 2750 0 50 ~ 0
P11_UART_TX
Text Label 6350 2850 0 50 ~ 0
P11_UART_RX
Text HLabel 3100 1350 0 50 Input ~ 0
Text HLabel 2950 1350 0 50 Input ~ 0
12V0
Wire Wire Line
3100 1350 3200 1350
Text HLabel 3100 1450 0 50 Input ~ 0
2950 1350 3050 1350
Text HLabel 2950 1450 0 50 Input ~ 0
3V3
Wire Wire Line
3100 1450 3200 1450
Text Label 3100 1550 2 50 ~ 0
2950 1450 3050 1450
Text Label 2950 1550 2 50 ~ 0
GND
Wire Wire Line
3100 1550 3200 1550
Text HLabel 3150 3050 0 50 BiDi ~ 0
2950 1550 3050 1550
Text HLabel 3000 3050 0 50 BiDi ~ 0
I2C_SDA
Wire Wire Line
3150 3050 3200 3050
Text HLabel 3150 3150 0 50 Input ~ 0
3000 3050 3050 3050
Text HLabel 3000 3150 0 50 Input ~ 0
I2C_SCL
Wire Wire Line
3150 3150 3200 3150
3000 3150 3050 3150
Text HLabel 6600 3350 2 50 Input ~ 0
EXT_TRIG_1_P
Text HLabel 6600 3450 2 50 Input ~ 0
@@ -365,83 +341,59 @@ GTX_TRIG_OUT_P
Text HLabel 5000 4350 0 50 Output ~ 0
GTX_TRIG_OUT_N
$Sheet
S 1400 1300 1350 1950
S 1100 1300 1350 1950
U 5F2B9784
F0 "Left Pods" 50
F1 "leftpods.sch" 50
F2 "POD0_UART_TX" O L 1400 1750 50
F3 "POD0_UART_RX" I L 1400 1850 50
F4 "POD1_UART_TX" O L 1400 1950 50
F5 "POD1_UART_RX" I L 1400 2050 50
F6 "POD2_UART_TX" O L 1400 2150 50
F7 "POD2_UART_RX" I L 1400 2250 50
F8 "POD3_UART_TX" O L 1400 2350 50
F9 "POD3_UART_RX" I L 1400 2450 50
F10 "POD4_UART_TX" O L 1400 2550 50
F11 "POD4_UART_RX" I L 1400 2650 50
F12 "POD5_UART_TX" O L 1400 2750 50
F13 "POD5_UART_RX" I L 1400 2850 50
F14 "P0_12V0" I R 2750 1750 50
F15 "P1_12V0" I R 2750 1950 50
F16 "P2_12V0" I R 2750 2150 50
F17 "P3_12V0" I R 2750 2350 50
F18 "P4_12V0" I R 2750 2550 50
F19 "P5_12V0" I R 2750 2750 50
F20 "P0_PRESENT" O R 2750 1850 50
F21 "P1_PRESENT" O R 2750 2050 50
F22 "P2_PRESENT" O R 2750 2250 50
F23 "P3_PRESENT" O R 2750 2450 50
F24 "P4_PRESENT" O R 2750 2650 50
F25 "P5_PRESENT" O R 2750 2850 50
F26 "GND" I L 1400 1350 50
F2 "POD0_UART_TX" O L 1100 1750 50
F3 "POD0_UART_RX" I L 1100 1850 50
F4 "POD1_UART_TX" O L 1100 1950 50
F5 "POD1_UART_RX" I L 1100 2050 50
F6 "POD2_UART_TX" O L 1100 2150 50
F7 "POD2_UART_RX" I L 1100 2250 50
F8 "POD3_UART_TX" O L 1100 2350 50
F9 "POD3_UART_RX" I L 1100 2450 50
F10 "POD4_UART_TX" O L 1100 2550 50
F11 "POD4_UART_RX" I L 1100 2650 50
F12 "POD5_UART_TX" O L 1100 2750 50
F13 "POD5_UART_RX" I L 1100 2850 50
F14 "P0_12V0" I R 2450 1750 50
F15 "P1_12V0" I R 2450 1950 50
F16 "P2_12V0" I R 2450 2150 50
F17 "P3_12V0" I R 2450 2350 50
F18 "P4_12V0" I R 2450 2550 50
F19 "P5_12V0" I R 2450 2750 50
F20 "P0_PRESENT" O R 2450 1850 50
F21 "P1_PRESENT" O R 2450 2050 50
F22 "P2_PRESENT" O R 2450 2250 50
F23 "P3_PRESENT" O R 2450 2450 50
F24 "P4_PRESENT" O R 2450 2650 50
F25 "P5_PRESENT" O R 2450 2850 50
F26 "GND" I L 1100 1350 50
$EndSheet
Wire Wire Line
2750 2850 3200 2850
Wire Wire Line
3200 2750 2750 2750
Wire Wire Line
2750 2650 3200 2650
Wire Wire Line
3200 2550 2750 2550
Wire Wire Line
2750 2450 3200 2450
Wire Wire Line
3200 2350 2750 2350
Wire Wire Line
2750 2250 3200 2250
Wire Wire Line
3200 2150 2750 2150
Wire Wire Line
2750 2050 3200 2050
Wire Wire Line
3200 1950 2750 1950
Wire Wire Line
2750 1850 3200 1850
Wire Wire Line
3200 1750 2750 1750
Text Label 1400 1750 2 50 ~ 0
Text Label 1100 1750 2 50 ~ 0
P0_UART_TX
Text Label 1400 1950 2 50 ~ 0
Text Label 1100 1950 2 50 ~ 0
P1_UART_TX
Text Label 1400 2150 2 50 ~ 0
Text Label 1100 2150 2 50 ~ 0
P2_UART_TX
Text Label 1400 2350 2 50 ~ 0
Text Label 1100 2350 2 50 ~ 0
P3_UART_TX
Text Label 1400 2550 2 50 ~ 0
Text Label 1100 2550 2 50 ~ 0
P4_UART_TX
Text Label 1400 2750 2 50 ~ 0
Text Label 1100 2750 2 50 ~ 0
P5_UART_TX
Text Label 1400 1850 2 50 ~ 0
Text Label 1100 1850 2 50 ~ 0
P0_UART_RX
Text Label 1400 2050 2 50 ~ 0
Text Label 1100 2050 2 50 ~ 0
P1_UART_RX
Text Label 1400 2250 2 50 ~ 0
Text Label 1100 2250 2 50 ~ 0
P2_UART_RX
Text Label 1400 2450 2 50 ~ 0
Text Label 1100 2450 2 50 ~ 0
P3_UART_RX
Text Label 1400 2650 2 50 ~ 0
Text Label 1100 2650 2 50 ~ 0
P4_UART_RX
Text Label 1400 2850 2 50 ~ 0
Text Label 1100 2850 2 50 ~ 0
P5_UART_RX
Text HLabel 6600 4250 2 50 Output ~ 0
TRIG_OUT_P
@@ -455,12 +407,168 @@ Text HLabel 6600 1450 2 50 Input ~ 0
1V2
Wire Wire Line
6600 1450 6350 1450
Text Label 1400 1350 2 50 ~ 0
Text Label 1100 1350 2 50 ~ 0
GND
Text HLabel 5000 1350 0 50 Input ~ 0
5V0
Text HLabel 5000 1450 0 50 Input ~ 0
0V5
Text HLabel 5000 1550 0 50 Input ~ 0
5V0_N
Wire Wire Line
2450 2850 3050 2850
Wire Wire Line
2450 2650 3050 2650
$Comp
L passive-azonenberg:FERRITE_SMALL FB11
U 1 1 619C130A
P 2750 1950
F 0 "FB11" H 2750 2050 60 0000 C CNN
F 1 "300R" H 2750 1950 60 0000 C CNN
F 2 "" H 2750 1950 60 0000 C CNN
F 3 "" H 2750 1950 60 0000 C CNN
1 2750 1950
-1 0 0 1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB13
U 1 1 619C1B8C
P 2750 2350
F 0 "FB13" H 2750 2450 60 0000 C CNN
F 1 "300R" H 2750 2350 60 0000 C CNN
F 2 "" H 2750 2350 60 0000 C CNN
F 3 "" H 2750 2350 60 0000 C CNN
1 2750 2350
-1 0 0 1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB14
U 1 1 619C1EF8
P 2750 2550
F 0 "FB14" H 2750 2650 60 0000 C CNN
F 1 "300R" H 2750 2550 60 0000 C CNN
F 2 "" H 2750 2550 60 0000 C CNN
F 3 "" H 2750 2550 60 0000 C CNN
1 2750 2550
-1 0 0 1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB15
U 1 1 619C21E5
P 2750 2750
F 0 "FB15" H 2750 2850 60 0000 C CNN
F 1 "300R" H 2750 2750 60 0000 C CNN
F 2 "" H 2750 2750 60 0000 C CNN
F 3 "" H 2750 2750 60 0000 C CNN
1 2750 2750
-1 0 0 1
$EndComp
Wire Wire Line
4400 1850 5000 1850
Wire Wire Line
4400 2050 5000 2050
Wire Wire Line
4400 2250 5000 2250
Wire Wire Line
4400 2450 5000 2450
Wire Wire Line
4400 2650 5000 2650
Wire Wire Line
4400 2850 5000 2850
$Comp
L passive-azonenberg:FERRITE_SMALL FB16
U 1 1 619CB54A
P 4700 1750
F 0 "FB16" H 4700 1850 60 0000 C CNN
F 1 "300R" H 4700 1750 60 0000 C CNN
F 2 "" H 4700 1750 60 0000 C CNN
F 3 "" H 4700 1750 60 0000 C CNN
1 4700 1750
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB17
U 1 1 619CBBFF
P 4700 1950
F 0 "FB17" H 4700 2050 60 0000 C CNN
F 1 "300R" H 4700 1950 60 0000 C CNN
F 2 "" H 4700 1950 60 0000 C CNN
F 3 "" H 4700 1950 60 0000 C CNN
1 4700 1950
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB18
U 1 1 619CBE83
P 4700 2150
F 0 "FB18" H 4700 2250 60 0000 C CNN
F 1 "300R" H 4700 2150 60 0000 C CNN
F 2 "" H 4700 2150 60 0000 C CNN
F 3 "" H 4700 2150 60 0000 C CNN
1 4700 2150
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB19
U 1 1 619CC12A
P 4700 2350
F 0 "FB19" H 4700 2450 60 0000 C CNN
F 1 "300R" H 4700 2350 60 0000 C CNN
F 2 "" H 4700 2350 60 0000 C CNN
F 3 "" H 4700 2350 60 0000 C CNN
1 4700 2350
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB20
U 1 1 619CC3A8
P 4700 2550
F 0 "FB20" H 4700 2650 60 0000 C CNN
F 1 "300R" H 4700 2550 60 0000 C CNN
F 2 "" H 4700 2550 60 0000 C CNN
F 3 "" H 4700 2550 60 0000 C CNN
1 4700 2550
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB21
U 1 1 619CC6A1
P 4700 2750
F 0 "FB21" H 4700 2850 60 0000 C CNN
F 1 "300R" H 4700 2750 60 0000 C CNN
F 2 "" H 4700 2750 60 0000 C CNN
F 3 "" H 4700 2750 60 0000 C CNN
1 4700 2750
1 0 0 -1
$EndComp
$Comp
L passive-azonenberg:FERRITE_SMALL FB10
U 1 1 619B1A52
P 2750 1750
F 0 "FB10" H 2750 1850 60 0000 C CNN
F 1 "300R" H 2750 1750 60 0000 C CNN
F 2 "" H 2750 1750 60 0000 C CNN
F 3 "" H 2750 1750 60 0000 C CNN
1 2750 1750
-1 0 0 1
$EndComp
Wire Wire Line
2450 2050 3050 2050
Wire Wire Line
2450 2250 3050 2250
Wire Wire Line
2450 1850 3050 1850
Wire Wire Line
2450 2450 3050 2450
$Comp
L passive-azonenberg:FERRITE_SMALL FB12
U 1 1 619C179E
P 2750 2150
F 0 "FB12" H 2750 2250 60 0000 C CNN
F 1 "300R" H 2750 2150 60 0000 C CNN
F 2 "" H 2750 2150 60 0000 C CNN
F 3 "" H 2750 2150 60 0000 C CNN
1 2750 2150
-1 0 0 1
$EndComp
$EndSCHEMATC
18 changes: 16 additions & 2 deletions boards/MAXWELL/maxwell-main/maxwell-main-cache.lib
View file
Original file line number Diff line number Diff line change
@@ -616,6 +616,20 @@ X GND_OUT 4 1000 50 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# passive-azonenberg_FERRITE_SMALL
#
DEF passive-azonenberg_FERRITE_SMALL FB 0 40 Y Y 1 F N
F0 "FB" 0 100 60 H V C CNN
F1 "passive-azonenberg_FERRITE_SMALL" 0 -100 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -150 50 150 -50 0 1 0 N
X ~ 1 300 0 150 L 50 50 1 1 w
X ~ 2 -300 0 150 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# passive-azonenberg_INDUCTOR_PWROUT
#
DEF passive-azonenberg_INDUCTOR_PWROUT L 0 40 N N 1 F N
@@ -1322,8 +1336,8 @@ X VCCO 13 -200 1150 200 R 50 50 1 1 W
X GND 14 -200 950 200 R 50 50 1 1 W
X SEL 15 -200 650 200 R 50 50 1 1 I
X IN0_P 16 -200 450 200 R 50 50 1 1 I
X VT0 2 850 1450 200 L 50 50 1 1 W
X VT1 3 850 1350 200 L 50 50 1 1 W
X VT0 2 850 1450 200 L 50 50 1 1 P
X VT1 3 850 1350 200 L 50 50 1 1 P
X IN1_P 4 -200 150 200 R 50 50 1 1 I
X IN1_N 5 -200 50 200 R 50 50 1 1 I
X EQ 6 850 1150 200 L 50 50 1 1 I
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/maxwell-main.sch
View file
Original file line number Diff line number Diff line change
@@ -219,7 +219,7 @@ Text Label 6300 2300 0 50 ~ 0
Text Label 6300 2400 0 50 ~ 0
1V8
Text Label 6300 2600 0 50 ~ 0
1V0
1V0_1
Text Label 6300 2800 0 50 ~ 0
GND
Wire Wire Line
4 changes: 2 additions & 2 deletions boards/MAXWELL/maxwell-main/podpower.sch
View file
Original file line number Diff line number Diff line change
@@ -50,8 +50,6 @@ Text HLabel 7250 2000 0 50 Input ~ 0
GND
Text Label 7700 2200 2 50 ~ 0
P0_PWREN
Text HLabel 10200 1500 2 50 Output ~ 0
P0_12V0
Wire Wire Line
9400 1500 9250 1500
Wire Wire Line
@@ -2337,4 +2335,6 @@ Wire Wire Line
2100 7950 2100 7850
Text Notes 8850 8250 0 50 ~ 0
TODO: EMI filters on output 12V lines
Text HLabel 10200 1500 2 50 Output ~ 0
P0_12V0
$EndSCHEMATC