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Implement r_rst output signal for AsyncFIFO #367

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merged 3 commits into from Apr 24, 2020

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awygle
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@awygle awygle commented Apr 24, 2020

This is the last bit of #181 which still needs to be done before that issue can be closed.

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codecov bot commented Apr 24, 2020

Codecov Report

Merging #367 into master will increase coverage by 0.02%.
The diff coverage is 100.00%.

Impacted file tree graph

@@            Coverage Diff             @@
##           master     #367      +/-   ##
==========================================
+ Coverage   82.56%   82.58%   +0.02%     
==========================================
  Files          35       35              
  Lines        5952     5962      +10     
  Branches     1211     1213       +2     
==========================================
+ Hits         4914     4924      +10     
+ Misses        872      871       -1     
- Partials      166      167       +1     
Impacted Files Coverage Δ
nmigen/lib/fifo.py 92.97% <100.00%> (+0.19%) ⬆️
nmigen/build/run.py 31.25% <0.00%> (ø)
nmigen/hdl/ir.py 95.47% <0.00%> (+0.05%) ⬆️

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nmigen/lib/fifo.py Outdated Show resolved Hide resolved
r_attributes="",
r_attributes="""
r_rst : out
Asserted when the FIFO is reset by the write-domain reset.
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Asserted when? That implies to me that it's something like a 1-clock pulse. In reality it is asserted while, right?

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I wrote while initially, but the write domain reset pulse can technically be shorter than a read domain clock cycle, so I felt like it was inaccurate. Probably needlessly pedantic though - you're right that when implies a single pulse (which we could do, i guess).

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I think holding it while the reset is asserted is a lot more useful, since you can go to a pulse from that but not the other way around.

Regaring pedantry, I think pedantry around CDC is pretty much a necessity. I think it would be very useful if we wrote that it is asserted "while the write-domain reset is, but no less than one read-domain clock cycle" or something like that.

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(No less than two in practice, but do we want to commit to that?)

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OK, I agree with that. "Asserted while the FIFO is being reset by the write-domain reset (for at least one read-domain clock cycle)"

awygle and others added 2 commits April 24, 2020 15:06
@whitequark whitequark merged commit ba79b0c into amaranth-lang:master Apr 24, 2020
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Thank you! This is a very nice addition that will enable Glasgow to, finally, support async applets properly.

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2 participants