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base repository: amaranth-lang/amaranth
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compare: ba79b0cdc675
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Apr 24, 2020

  1. lib.fifo: add r_rst output for AsyncFIFO{,Buffered}. 

    Fixes #181.
    @awygle
    awygle authored Apr 24, 2020
    Copy the full SHA
    ba79b0c View commit details
Showing with 17 additions and 3 deletions.
  1. +17 −3 nmigen/lib/fifo.py
20 changes: 17 additions & 3 deletions nmigen/lib/fifo.py
View file
Original file line number Diff line number Diff line change
@@ -279,7 +279,11 @@ class AsyncFIFO(Elaboratable, FIFOInterface):
Always set.
""".strip(),
r_data_valid="Valid if ``r_rdy`` is asserted.",
r_attributes="",
r_attributes="""
r_rst : Signal, out
Asserted while the FIFO is being reset by the write-domain reset (for at least one
read-domain clock cycle).
""".strip(),
w_attributes="")

def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
@@ -295,6 +299,7 @@ def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_dep
depth_bits = 0
super().__init__(width=width, depth=depth, fwft=True)

self.r_rst = Signal()
self._r_domain = r_domain
self._w_domain = w_domain
self._ctr_bits = depth_bits + 1
@@ -393,11 +398,14 @@ def elaborate(self, platform):
# counter in read domain.
rst_dec = m.submodules.rst_dec = \
GrayDecoder(self._ctr_bits)
m.d.comb += rst_dec.i.eq(produce_r_gry),
m.d.comb += rst_dec.i.eq(produce_r_gry)
with m.If(r_rst):
m.d.comb += r_empty.eq(1)
m.d[self._r_domain] += consume_r_gry.eq(produce_r_gry)
m.d[self._r_domain] += consume_r_bin.eq(rst_dec.o)
m.d[self._r_domain] += self.r_rst.eq(1)
with m.Else():
m.d[self._r_domain] += self.r_rst.eq(0)

if platform == "formal":
with m.If(Initial()):
@@ -436,7 +444,11 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
Always set.
""".strip(),
r_data_valid="Valid if ``r_rdy`` is asserted.",
r_attributes="",
r_attributes="""
r_rst : Signal, out
Asserted while the FIFO is being reset by the write-domain reset (for at least one
read-domain clock cycle).
""".strip(),
w_attributes="")

def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
@@ -450,6 +462,7 @@ def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_dep
.format(depth)) from None
super().__init__(width=width, depth=depth, fwft=True)

self.r_rst = Signal()
self._r_domain = r_domain
self._w_domain = w_domain

@@ -475,6 +488,7 @@ def elaborate(self, platform):
m.d[self._r_domain] += [
self.r_data.eq(fifo.r_data),
self.r_rdy.eq(fifo.r_rdy),
self.r_rst.eq(fifo.r_rst),
]
m.d.comb += [
fifo.r_en.eq(1)