Vendor Tools IO placement error #1429
Description
The following error shows up from time to time on the Vendor tools CI, regarding the baselitex test:
FAILED: cd /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/build/xc/xc7/tests/soc/litex/base/baselitex_arty/artix7-xc7a50t-virt-xc7a50t-test && /usr/bin/cmake -E remove -f baselitex_arty/artix7-xc7a50t-virt-xc7a50t-test/design_baselitex_arty_vivado.dcp && /usr/bin/cmake -E remove -f baselitex_arty/artix7-xc7a50t-virt-xc7a50t-test/design_baselitex_arty_vivado.xpr && /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/third_party/prjxray/utils/vivado.sh -mode batch -source /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/build/xc/xc7/tests/soc/litex/base/baselitex_arty_vivado_runme.tcl > /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/build/xc/xc7/tests/soc/litex/base/baselitex_arty/artix7-xc7a50t-virt-xc7a50t-test/vivado.stdout.log
ERROR: [Place 30-294] The following IO terminals are loads of BUFIO/BUFR/BUFH
and they should be placed to the same clock region as BUFIO/BUFR/BUFH instance.
They have incompatible IO Standards that makes their placement illegal
IO Standard1: SioStd: DIFF_SSTL135 VCCO = 1.35 Termination: 0 TermDir: Out BufioId: 2 Bank: 34 Placed LVDS
List of IO terminals :
Term: ddram_dqs_p[0]
Term: ddram_dqs_n[0]
Term: ddram_dqs_p[1]
Term: ddram_dqs_n[1]
Term: ddram_clk_p
Term: ddram_clk_n
IO Standard2: SioStd: LVCMOS33 VCCO = 3.3 Termination: 0 TermDir: Out BufioId: 2 Bank: 15 Drv: 12 Placed
List of IO terminals :
Term: eth_ref_clk
ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 14 | 50 | 2 | LVCMOS33(2) | | | +3.30 | YES | |
| 15 | 50 | 16 | LVCMOS33(16) | | | +3.30 | YES | |
| 16 | 10 | 2 | LVCMOS33(2) | | | +3.30 | YES | |
| 34 | 50 | 48 | SSTL135(42) DIFF_SSTL135(6) | _IOI3_X113Y26_IDELAYCTRL_X1Y0_IDELAYCTRL | +0.68 | +1.35 | YES | |
| 35 | 50 | 4 | LVCMOS33(4) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 210 | 72 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 14 | led[2] | LVCMOS33 | IOB_X0Y2 | T9 | |
| | led[3] | LVCMOS33 | IOB_X0Y1 | T10 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 15 | eth_clocks_rx | LVCMOS33 | IOB_X0Y72 | F15 | |
| | eth_clocks_tx | LVCMOS33 | IOB_X0Y74 | H16 | |
| | eth_mdc | LVCMOS33 | IOB_X0Y71 | F16 | |
| | eth_mdio | LVCMOS33 | IOB_X0Y66 | K13 | |
| | eth_ref_clk | LVCMOS33 | IOB_X0Y56 | G18 | |
| | eth_rst_n | LVCMOS33 | IOB_X0Y60 | C16 | |
| | eth_rx_data[0] | LVCMOS33 | IOB_X0Y57 | D18 | |
| | eth_rx_data[1] | LVCMOS33 | IOB_X0Y68 | E17 | |
| | eth_rx_data[2] | LVCMOS33 | IOB_X0Y58 | E18 | |
| | eth_rx_data[3] | LVCMOS33 | IOB_X0Y63 | G17 | |
| | eth_rx_dv | LVCMOS33 | IOB_X0Y73 | G16 | |
| | eth_tx_data[0] | LVCMOS33 | IOB_X0Y70 | H14 | |
| | eth_tx_data[1] | LVCMOS33 | IOB_X0Y62 | J14 | |
| | eth_tx_data[2] | LVCMOS33 | IOB_X0Y65 | J13 | |
| | eth_tx_data[3] | LVCMOS33 | IOB_X0Y64 | H17 | |
| | eth_tx_en | LVCMOS33 | IOB_X0Y61 | H15 | * |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 16 | serial_rx | LVCMOS33 | IOB_X0Y121 | A9 | |
| | serial_tx | LVCMOS33 | IOB_X0Y111 | D10 | * |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34 | ddram_clk_p | DIFF_SSTL135 | IOB_X1Y8 | U9 | |
| | ddram_clk_n | DIFF_SSTL135 | IOB_X1Y7 | V9 | |
| | ddram_dqs_p[0] | DIFF_SSTL135 | IOB_X1Y44 | N2 | |
| | ddram_dqs_n[0] | DIFF_SSTL135 | IOB_X1Y43 | N1 | |
| | ddram_dqs_p[1] | DIFF_SSTL135 | IOB_X1Y32 | U2 | |
| | ddram_dqs_n[1] | DIFF_SSTL135 | IOB_X1Y31 | V2 | |
| | ddram_a[0] | SSTL135 | IOB_X1Y19 | R2 | VRef=+0.68 |
| | ddram_a[10] | SSTL135 | IOB_X1Y12 | R6 | VRef=+0.68 |
| | ddram_a[11] | SSTL135 | IOB_X1Y5 | U6 | VRef=+0.68 |
| | ddram_a[12] | SSTL135 | IOB_X1Y3 | T6 | VRef=+0.68 |
| | ddram_a[13] | SSTL135 | IOB_X1Y1 | T8 | VRef=+0.68 |
| | ddram_a[1] | SSTL135 | IOB_X1Y14 | M6 | VRef=+0.68 |
| | ddram_a[2] | SSTL135 | IOB_X1Y17 | N4 | VRef=+0.68 |
| | ddram_a[3] | SSTL135 | IOB_X1Y15 | T1 | VRef=+0.68 |
| | ddram_a[4] | SSTL135 | IOB_X1Y13 | N6 | VRef=+0.68 |
| | ddram_a[5] | SSTL135 | IOB_X1Y4 | R7 | VRef=+0.68 |
| | ddram_a[6] | SSTL135 | IOB_X1Y9 | V6 | VRef=+0.68 |
| | ddram_a[7] | SSTL135 | IOB_X1Y6 | U7 | VRef=+0.68 |
| | ddram_a[8] | SSTL135 | IOB_X1Y2 | R8 | VRef=+0.68 |
| | ddram_a[9] | SSTL135 | IOB_X1Y10 | V7 | VRef=+0.68 |
| | ddram_ba[0] | SSTL135 | IOB_X1Y16 | R1 | VRef=+0.68 |
| | ddram_ba[1] | SSTL135 | IOB_X1Y22 | P4 | VRef=+0.68 |
| | ddram_ba[2] | SSTL135 | IOB_X1Y20 | P2 | VRef=+0.68 |
| | ddram_cas_n | SSTL135 | IOB_X1Y18 | M4 | VRef=+0.68 |
| | ddram_cke | SSTL135 | IOB_X1Y24 | N5 | VRef=+0.68 |
| | ddram_cs_n | SSTL135 | IOB_X1Y0 | U8 | VRef=+0.68 |
| | ddram_dm[0] | SSTL135 | IOB_X1Y48 | L1 | VRef=+0.68 |
| | ddram_dm[1] | SSTL135 | IOB_X1Y36 | U1 | VRef=+0.68 |
| | ddram_dq[0] | SSTL135 | IOB_X1Y40 | K5 | VRef=+0.68 |
| | ddram_dq[10] | SSTL135 | IOB_X1Y34 | U4 | VRef=+0.68 |
| | ddram_dq[11] | SSTL135 | IOB_X1Y30 | V5 | VRef=+0.68 |
| | ddram_dq[12] | SSTL135 | IOB_X1Y35 | V1 | VRef=+0.68 |
| | ddram_dq[13] | SSTL135 | IOB_X1Y27 | T3 | VRef=+0.68 |
| | ddram_dq[14] | SSTL135 | IOB_X1Y33 | U3 | VRef=+0.68 |
| | ddram_dq[15] | SSTL135 | IOB_X1Y28 | R3 | VRef=+0.68 |
| | ddram_dq[1] | SSTL135 | IOB_X1Y45 | L3 | VRef=+0.68 |
| | ddram_dq[2] | SSTL135 | IOB_X1Y46 | K3 | VRef=+0.68 |
| | ddram_dq[3] | SSTL135 | IOB_X1Y38 | L6 | VRef=+0.68 |
| | ddram_dq[4] | SSTL135 | IOB_X1Y42 | M3 | VRef=+0.68 |
| | ddram_dq[5] | SSTL135 | IOB_X1Y47 | M1 | VRef=+0.68 |
| | ddram_dq[6] | SSTL135 | IOB_X1Y39 | L4 | VRef=+0.68 |
| | ddram_dq[7] | SSTL135 | IOB_X1Y41 | M2 | VRef=+0.68 |
| | ddram_dq[8] | SSTL135 | IOB_X1Y29 | V4 | VRef=+0.68 |
| | ddram_dq[9] | SSTL135 | IOB_X1Y26 | T5 | VRef=+0.68 |
| | ddram_odt | SSTL135 | IOB_X1Y11 | R5 | VRef=+0.68* |
| | ddram_ras_n | SSTL135 | IOB_X1Y21 | P3 | VRef=+0.68 |
| | ddram_reset_n | SSTL135 | IOB_X1Y49 | K6 | VRef=+0.68 |
| | ddram_we_n | SSTL135 | IOB_X1Y23 | P5 | VRef=+0.68 |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | clk100 | LVCMOS33 | IOB_X1Y76 | E3 | |
| | cpu_reset | LVCMOS33 | IOB_X1Y68 | C2 | |
| | led[0] | LVCMOS33 | IOB_X1Y51 | H5 | |
| | led[1] | LVCMOS33 | IOB_X1Y50 | J5 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
Still unknown the reason behind this behaviour which seems to be "randomic"
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acomodi commentedon Apr 28, 2020
To reproduce the issue the following bitstream can be used in the fasm2bels step:
top.bit.zip
litghost commentedon Jul 6, 2020
This error appears to be something that should be fixed in the clock placement logic.