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"OpenTitan RTL synthesis with Yosys" in hardenedlinux #1465

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rw1nkler opened this issue May 5, 2020 · 0 comments
Open

"OpenTitan RTL synthesis with Yosys" in hardenedlinux #1465

rw1nkler opened this issue May 5, 2020 · 0 comments

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@rw1nkler
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rw1nkler commented May 5, 2020

I was asked to follow the tutorial available at [LINK]

I have completed the tutorial successfully and obtained the .blif file. The presented approach to sv2v is different than those used for OpenTitan (#1442). Previously, I was converting files one-by-one. It will be worth to compare the netlists obtained using the approach presented in the tutorial, with netlist obtained from converting file one-by-one.

However, this tutorial uses the design variant dedicated for simulation purposes, so additional changes need to be added for FPGA variant conversion.

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