Multiple mapped tiles when creating synth io tiles #1538
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This issue seems to only occurs when trying to place synth tiles at a location that borders a clock region boundary. Do these tile names get mapped both to the actual tile coord and the break tile coord? |
This was referenced Jun 23, 2020
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Added a synth tile definition to the design.json as follows:
{ "name": "dout[8]", "node": "INT_R_X23Y100/LH3", "pin": "H7", "wire": "INT_INTERFACE_R_X23Y100/INT_INTERFACE_LH3", "wires_outside_roi": [ ] }And building the synth tiles gives the following error:
File "/scratch/safe/butta/symbiflow-arch-defs.syn/xc/common/utils/prjxray_create_synth_tiles.py", line 26, in map_tile_to_vpr_coord assert len(mapped_tiles) == 1, tile AssertionError: INT_INTERFACE_R_X23Y100I know this is not a normal location used as a synth tile, but is this a location I should be able to place a synth tile? Is mapping to multiple vpr coordinates the correct result in this situation or a bug?
Link to branch containing these changes: synth-tile-errors
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