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base repository: azonenberg/starshipraider
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base: a165559aa51c
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head repository: azonenberg/starshipraider
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compare: 10bcce1edb61
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  • 1 commit
  • 14 files changed
  • 1 contributor

Commits on Jun 16, 2020

  1. Left pods

    azonenberg committed Jun 16, 2020
    Copy the full SHA
    10bcce1 View commit details
12 changes: 6 additions & 6 deletions boards/MAXWELL/maxwell-main/clocking.sch
Original file line number Diff line number Diff line change
@@ -14,32 +14,32 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
L special-azonenberg:LMK04806 U?
L special-azonenberg:LMK04806 U36
U 1 1 5EF9E8C0
P 1800 5100
F 0 "U?" H 2400 9375 50 0000 C CNN
F 0 "U36" H 2400 9375 50 0000 C CNN
F 1 "LMK04806" H 2400 9284 50 0000 C CNN
F 2 "" H 1800 5100 50 0001 C CNN
F 3 "" H 1800 5100 50 0001 C CNN
1 1800 5100
1 0 0 -1
$EndComp
$Comp
L special-azonenberg:LMK04806 U?
L special-azonenberg:LMK04806 U36
U 2 1 5EFA0009
P 4500 5100
F 0 "U?" H 5075 6875 50 0000 C CNN
F 0 "U36" H 5075 6875 50 0000 C CNN
F 1 "LMK04806" H 5075 6784 50 0000 C CNN
F 2 "" H 4500 5100 50 0001 C CNN
F 3 "" H 4500 5100 50 0001 C CNN
2 4500 5100
1 0 0 -1
$EndComp
$Comp
L special-azonenberg:LMK04806 U?
L special-azonenberg:LMK04806 U36
U 3 1 5EFA1019
P 6600 5100
F 0 "U?" H 7418 5651 50 0000 L CNN
F 0 "U36" H 7418 5651 50 0000 L CNN
F 1 "LMK04806" H 7418 5560 50 0000 L CNN
F 2 "" H 6600 5100 50 0001 C CNN
F 3 "" H 6600 5100 50 0001 C CNN
8 changes: 4 additions & 4 deletions boards/MAXWELL/maxwell-main/fpgasupport.sch
Original file line number Diff line number Diff line change
@@ -14,21 +14,21 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
L xilinx-azonenberg:XILINX_JTAG J?
L xilinx-azonenberg:XILINX_JTAG J10
U 1 1 5EFC9A56
P 1050 2150
F 0 "J?" H 1769 2858 60 0000 L CNN
F 0 "J10" H 1769 2858 60 0000 L CNN
F 1 "XILINX_JTAG" H 1769 2752 60 0000 L CNN
F 2 "" H 1050 2150 60 0000 C CNN
F 3 "" H 1050 2150 60 0000 C CNN
1 1050 2150
1 0 0 -1
$EndComp
$Comp
L memory-azonenberg:W25Q80BV U?
L memory-azonenberg:W25Q80BV U34
U 1 1 5EFDEE77
P 6200 3500
F 0 "U?" H 6200 4187 60 0000 C CNN
F 0 "U34" H 6200 4187 60 0000 C CNN
F 1 "S25FL128LAGNFV010" H 6200 4081 60 0000 C CNN
F 2 "" H 6200 3500 60 0000 C CNN
F 3 "" H 6200 3500 60 0000 C CNN
88 changes: 80 additions & 8 deletions boards/MAXWELL/maxwell-main/inputs.sch
Original file line number Diff line number Diff line change
@@ -55,8 +55,8 @@ P 9300 5800
AR Path="/5F049B6D/5F293D5C" Ref="U?" Part="2"
AR Path="/5F080E90/5F293D5C" Ref="U?" Part="3"
AR Path="/5EDD723A/5F0BA462/5F293D5C" Ref="U?" Part="4"
AR Path="/5EDD723A/5F293D5C" Ref="U?" Part="3"
F 0 "U?" H 9300 5750 50 0000 L CNN
AR Path="/5EDD723A/5F293D5C" Ref="U4" Part="3"
F 0 "U4" H 9300 5750 50 0000 L CNN
F 1 "XC7S6-1FTGB196C" H 9300 5650 50 0000 L CNN
F 2 "" H 9300 5800 50 0001 C CNN
F 3 "" H 9300 5800 50 0001 C CNN
@@ -92,12 +92,6 @@ S7_QSPI_DQ2
Text Label 9100 1250 2 50 ~ 0
S7_QSPI_DQ3
$Sheet
S 1400 1300 1350 1950
U 5F2B9784
F0 "Left Pods" 50
F1 "leftpods.sch" 50
$EndSheet
$Sheet
S 5000 1300 1350 3150
U 5F2BB4CD
F0 "Right Pods" 50
@@ -374,4 +368,82 @@ Text HLabel 5000 4250 0 50 Output ~ 0
GTX_TRIG_OUT_P
Text HLabel 5000 4350 0 50 Output ~ 0
GTX_TRIG_OUT_N
$Sheet
S 1400 1300 1350 1950
U 5F2B9784
F0 "Left Pods" 50
F1 "leftpods.sch" 50
F2 "POD0_UART_TX" O L 1400 1750 50
F3 "POD0_UART_RX" I L 1400 1850 50
F4 "POD1_UART_TX" O L 1400 1950 50
F5 "POD1_UART_RX" I L 1400 2050 50
F6 "POD2_UART_TX" O L 1400 2150 50
F7 "POD2_UART_RX" I L 1400 2250 50
F8 "POD3_UART_TX" O L 1400 2350 50
F9 "POD3_UART_RX" I L 1400 2450 50
F10 "POD4_UART_TX" O L 1400 2550 50
F11 "POD4_UART_RX" I L 1400 2650 50
F12 "POD5_UART_TX" O L 1400 2750 50
F13 "POD5_UART_RX" I L 1400 2850 50
F14 "P0_12V0" I R 2750 1750 50
F15 "P1_12V0" I R 2750 1950 50
F16 "P2_12V0" I R 2750 2150 50
F17 "P3_12V0" I R 2750 2350 50
F18 "P4_12V0" I R 2750 2550 50
F19 "P5_12V0" I R 2750 2750 50
F20 "P0_PRESENT" O R 2750 1850 50
F21 "P1_PRESENT" O R 2750 2050 50
F22 "P2_PRESENT" O R 2750 2250 50
F23 "P3_PRESENT" O R 2750 2450 50
F24 "P4_PRESENT" O R 2750 2650 50
F25 "P5_PRESENT" O R 2750 2850 50
$EndSheet
Wire Wire Line
2750 2850 3200 2850
Wire Wire Line
3200 2750 2750 2750
Wire Wire Line
2750 2650 3200 2650
Wire Wire Line
3200 2550 2750 2550
Wire Wire Line
2750 2450 3200 2450
Wire Wire Line
3200 2350 2750 2350
Wire Wire Line
2750 2250 3200 2250
Wire Wire Line
3200 2150 2750 2150
Wire Wire Line
2750 2050 3200 2050
Wire Wire Line
3200 1950 2750 1950
Wire Wire Line
2750 1850 3200 1850
Wire Wire Line
3200 1750 2750 1750
Text Label 1400 1750 2 50 ~ 0
P0_UART_TX
Text Label 1400 1950 2 50 ~ 0
P1_UART_TX
Text Label 1400 2150 2 50 ~ 0
P2_UART_TX
Text Label 1400 2350 2 50 ~ 0
P3_UART_TX
Text Label 1400 2550 2 50 ~ 0
P4_UART_TX
Text Label 1400 2750 2 50 ~ 0
P5_UART_TX
Text Label 1400 1850 2 50 ~ 0
P0_UART_RX
Text Label 1400 2050 2 50 ~ 0
P1_UART_RX
Text Label 1400 2250 2 50 ~ 0
P2_UART_RX
Text Label 1400 2450 2 50 ~ 0
P3_UART_RX
Text Label 1400 2650 2 50 ~ 0
P4_UART_RX
Text Label 1400 2850 2 50 ~ 0
P5_UART_RX
$EndSCHEMATC
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