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base repository: azonenberg/starshipraider
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head repository: azonenberg/starshipraider
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compare: a165559aa51c
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  • 1 commit
  • 10 files changed
  • 1 contributor

Commits on Jun 16, 2020

  1. Copy the full SHA
    a165559 View commit details
53 changes: 52 additions & 1 deletion boards/MAXWELL/maxwell-main/clocking.sch
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 13 15
Sheet 14 15
Title "MAXWELL Main Board"
Date "2020-06-15"
Rev "0.1"
@@ -51,5 +51,56 @@ S 6900 1450 1050 1500
U 5F303230
F0 "Trigger and Reference Inputs" 50
F1 "trigger.sch" 50
F2 "GND" I L 6900 2250 50
F3 "TRIG_IN_P" O L 6900 2000 50
F4 "TRIG_IN_N" O L 6900 2100 50
F5 "REF_IN_P" O L 6900 2400 50
F6 "REF_IN_N" O L 6900 2500 50
F7 "PPS_IN_P" O L 6900 2650 50
F8 "PPS_IN_N" O L 6900 2750 50
F9 "REF_OUT_P" I L 6900 1600 50
F10 "REF_OUT_N" I L 6900 1700 50
$EndSheet
Text HLabel 5050 1500 0 50 Output ~ 0
S7_CLK_P
Text HLabel 5050 1600 0 50 Output ~ 0
S7_CLK_N
Text HLabel 5050 1800 0 50 Output ~ 0
K7_CLK_P
Text HLabel 5050 1900 0 50 Output ~ 0
K7_CLK_N
Text HLabel 5050 1300 0 50 Output ~ 0
ETH_REFCLK
Text HLabel 5050 2050 0 50 Output ~ 0
LA_REFCLK_P
Text HLabel 5050 2150 0 50 Output ~ 0
LA_REFCLK_N
Text HLabel 5050 2350 0 50 Output ~ 0
SYNC_CLK_1_P
Text HLabel 5050 2450 0 50 Output ~ 0
SYNC_CLK_1_N
Text HLabel 5050 2650 0 50 Output ~ 0
SYNC_CLK_2_P
Text HLabel 5050 2750 0 50 Output ~ 0
SYNC_CLK_2_N
Text HLabel 5050 2900 0 50 Output ~ 0
XG_REFCLK_P
Text HLabel 5050 3000 0 50 Output ~ 0
XG_REFCLK_N
Text HLabel 8700 3250 0 50 Output ~ 0
EXT_TRIG_1_P
Text HLabel 8700 3350 0 50 Output ~ 0
EXT_TRIG_1_N
Text HLabel 8700 3550 0 50 Output ~ 0
EXT_TRIG_2_P
Text HLabel 8700 3650 0 50 Output ~ 0
EXT_TRIG_2_N
Text HLabel 8700 3850 0 50 Input ~ 0
TRIG_OUT_P
Text HLabel 8700 3950 0 50 Input ~ 0
TRIG_OUT_N
Text HLabel 8700 4150 0 50 Input ~ 0
GTX_TRIG_OUT_P
Text HLabel 8700 4250 0 50 Input ~ 0
GTX_TRIG_OUT_N
$EndSCHEMATC
294 changes: 256 additions & 38 deletions boards/MAXWELL/maxwell-main/inputs.sch
Original file line number Diff line number Diff line change
@@ -14,39 +14,39 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1050 3500 1150 1900
S 3200 1300 1350 1950
U 5F0BA462
F0 "Pod Power" 50
F1 "podpower.sch" 50
F2 "3V3" I L 1050 3650 50
F3 "12V0" I L 1050 3550 50
F4 "GND" I L 1050 3750 50
F5 "P0_12V0" O R 2200 3950 50
F6 "P0_PRESENT" I L 1050 3950 50
F7 "P1_PRESENT" I L 1050 4050 50
F8 "P2_PRESENT" I L 1050 4150 50
F9 "P3_PRESENT" I L 1050 4250 50
F10 "P4_PRESENT" I L 1050 4350 50
F11 "P5_PRESENT" I L 1050 4450 50
F12 "P6_PRESENT" I L 1050 4550 50
F13 "P7_PRESENT" I L 1050 4650 50
F14 "P8_PRESENT" I L 1050 4750 50
F15 "P9_PRESENT" I L 1050 4850 50
F16 "P10_PRESENT" I L 1050 4950 50
F17 "P11_PRESENT" I L 1050 5050 50
F18 "P1_12V0" O R 2200 4050 50
F19 "P2_12V0" O R 2200 4150 50
F20 "P3_12V0" O R 2200 4250 50
F21 "P4_12V0" O R 2200 4350 50
F22 "P5_12V0" O R 2200 4450 50
F23 "P6_12V0" O R 2200 4550 50
F24 "P7_12V0" O R 2200 4650 50
F25 "P8_12V0" O R 2200 4750 50
F26 "P9_12V0" O R 2200 4850 50
F27 "P10_12V0" O R 2200 4950 50
F28 "P11_12V0" O R 2200 5050 50
F29 "I2C_SDA" B L 1050 5250 50
F30 "I2C_SCL" I L 1050 5350 50
F2 "3V3" I L 3200 1450 50
F3 "12V0" I L 3200 1350 50
F4 "GND" I L 3200 1550 50
F5 "P0_12V0" O L 3200 1750 50
F6 "P0_PRESENT" I L 3200 1850 50
F7 "P1_PRESENT" I L 3200 2050 50
F8 "P2_PRESENT" I L 3200 2250 50
F9 "P3_PRESENT" I L 3200 2450 50
F10 "P4_PRESENT" I L 3200 2650 50
F11 "P5_PRESENT" I L 3200 2850 50
F12 "P6_PRESENT" I R 4550 1850 50
F13 "P7_PRESENT" I R 4550 2050 50
F14 "P8_PRESENT" I R 4550 2250 50
F15 "P9_PRESENT" I R 4550 2450 50
F16 "P10_PRESENT" I R 4550 2650 50
F17 "P11_PRESENT" I R 4550 2850 50
F18 "P1_12V0" O L 3200 1950 50
F19 "P2_12V0" O L 3200 2150 50
F20 "P3_12V0" O L 3200 2350 50
F21 "P4_12V0" O L 3200 2550 50
F22 "P5_12V0" O L 3200 2750 50
F23 "P6_12V0" O R 4550 1750 50
F24 "P7_12V0" O R 4550 1950 50
F25 "P8_12V0" O R 4550 2150 50
F26 "P9_12V0" O R 4550 2350 50
F27 "P10_12V0" O R 4550 2550 50
F28 "P11_12V0" O R 4550 2750 50
F29 "I2C_SDA" B L 3200 3050 50
F30 "I2C_SCL" I L 3200 3150 50
$EndSheet
$Comp
L xilinx-azonenberg:XC7Sx-FTGB196 U?
@@ -64,15 +64,22 @@ F 3 "" H 9300 5800 50 0001 C CNN
1 0 0 -1
$EndComp
$Sheet
S 3500 3600 1050 1500
S 5000 4750 1350 850
U 5F297DD1
F0 "IO FPGA" 50
F1 "iofpga.sch" 50
F2 "S7_QSPI_DQ0" B R 4550 3750 50
F3 "S7_QSPI_DQ1" B R 4550 3850 50
F4 "S7_QSPI_DQ2" B R 4550 3950 50
F5 "S7_QSPI_DQ3" B R 4550 4050 50
F6 "S7_QSPI_CS_N" I R 4550 3650 50
F2 "S7_QSPI_DQ0" B R 6350 4900 50
F3 "S7_QSPI_DQ1" B R 6350 5000 50
F4 "S7_QSPI_DQ2" B R 6350 5100 50
F5 "S7_QSPI_DQ3" B R 6350 5200 50
F6 "S7_QSPI_CS_N" I R 6350 4800 50
F7 "1V0" I L 5000 5000 50
F8 "1V8" I L 5000 4900 50
F9 "GND" I L 5000 5100 50
F10 "3V3" I L 5000 4800 50
F11 "S7_RST_N" I L 5000 5300 50
F12 "S7_INIT_B" B L 5000 5400 50
F13 "S7_DONE" O L 5000 5500 50
$EndSheet
Text Label 9100 1950 2 50 ~ 0
S7_QSPI_CS_N
@@ -85,16 +92,54 @@ S7_QSPI_DQ2
Text Label 9100 1250 2 50 ~ 0
S7_QSPI_DQ3
$Sheet
S 1050 1300 1100 1500
S 1400 1300 1350 1950
U 5F2B9784
F0 "Left Pods" 50
F1 "leftpods.sch" 50
$EndSheet
$Sheet
S 2550 1300 1000 1500
S 5000 1300 1350 3150
U 5F2BB4CD
F0 "Right Pods" 50
F1 "rightpods.sch" 50
F2 "K7_CLK_P" I R 6350 3050 50
F3 "K7_CLK_N" I R 6350 3150 50
F4 "POD6_UART_TX" O R 6350 1750 50
F5 "POD6_UART_RX" I R 6350 1850 50
F6 "POD7_UART_TX" O R 6350 1950 50
F7 "POD7_UART_RX" I R 6350 2050 50
F8 "POD8_UART_TX" O R 6350 2150 50
F9 "POD8_UART_RX" I R 6350 2250 50
F10 "POD9_UART_TX" O R 6350 2350 50
F11 "POD9_UART_RX" I R 6350 2450 50
F12 "POD10_UART_TX" O R 6350 2550 50
F13 "POD10_UART_RX" I R 6350 2650 50
F14 "POD11_UART_TX" O R 6350 2750 50
F15 "POD11_UART_RX" I R 6350 2850 50
F16 "2V5" I R 6350 1350 50
F17 "GND" I R 6350 1450 50
F18 "P6_12V0" I L 5000 1750 50
F19 "P7_12V0" I L 5000 1950 50
F20 "P8_12V0" I L 5000 2150 50
F21 "P9_12V0" I L 5000 2350 50
F22 "P10_12V0" I L 5000 2550 50
F23 "P11_12V0" I L 5000 2750 50
F24 "P6_PRESENT" O L 5000 1850 50
F25 "P7_PRESENT" O L 5000 2050 50
F26 "P8_PRESENT" O L 5000 2250 50
F27 "P9_PRESENT" O L 5000 2450 50
F28 "P10_PRESENT" O L 5000 2650 50
F29 "P11_PRESENT" O L 5000 2850 50
F30 "EXT_TRIG_P" I R 6350 3350 50
F31 "EXT_TRIG_N" I R 6350 3450 50
F32 "LA_REFCLK_P" I R 6350 3650 50
F33 "LA_REFCLK_N" I R 6350 3750 50
F34 "SYNC_CLK_P" I R 6350 3950 50
F35 "SYNC_CLK_N" I R 6350 4050 50
F36 "TRIG_OUT_P" O R 6350 4250 50
F37 "TRIG_OUT_N" O R 6350 4350 50
F38 "GTX_TRIG_OUT_P" O L 5000 4250 50
F39 "GTX_TRIG_OUT_N" O L 5000 4350 50
$EndSheet
Text Label 9100 1350 2 50 ~ 0
P0_UART_TX
@@ -156,4 +201,177 @@ Text Label 9100 4250 2 50 ~ 0
P11_UART_TX
Text Label 9100 4350 2 50 ~ 0
P11_UART_RX
Wire Wire Line
4550 1750 5000 1750
Wire Wire Line
5000 1850 4550 1850
Wire Wire Line
4550 1950 5000 1950
Wire Wire Line
5000 2050 4550 2050
Wire Wire Line
4550 2150 5000 2150
Wire Wire Line
5000 2250 4550 2250
Wire Wire Line
4550 2350 5000 2350
Wire Wire Line
5000 2450 4550 2450
Wire Wire Line
4550 2550 5000 2550
Wire Wire Line
5000 2650 4550 2650
Wire Wire Line
4550 2750 5000 2750
Wire Wire Line
5000 2850 4550 2850
Text HLabel 6600 3050 2 50 Input ~ 0
K7_CLK_P
Text HLabel 6600 3150 2 50 Input ~ 0
K7_CLK_N
Wire Wire Line
6600 3050 6350 3050
Wire Wire Line
6350 3150 6600 3150
Text HLabel 6600 1350 2 50 Input ~ 0
2V5
Wire Wire Line
6600 1350 6350 1350
Text HLabel 6600 1450 2 50 Input ~ 0
GND
Wire Wire Line
6600 1450 6350 1450
Text HLabel 4850 4800 0 50 Input ~ 0
3V3
Wire Wire Line
4850 4800 5000 4800
Text HLabel 4850 4900 0 50 Input ~ 0
1V8
Wire Wire Line
4850 4900 5000 4900
Text HLabel 4850 5000 0 50 Input ~ 0
1V0
Wire Wire Line
4850 5000 5000 5000
Text Label 4850 5100 2 50 ~ 0
GND
Wire Wire Line
4850 5100 5000 5100
Text Label 6350 4900 0 50 ~ 0
S7_QSPI_DQ0
Text Label 6350 5000 0 50 ~ 0
S7_QSPI_DQ1
Text Label 6350 5100 0 50 ~ 0
S7_QSPI_DQ2
Text Label 6350 5200 0 50 ~ 0
S7_QSPI_DQ3
Text Label 6350 4800 0 50 ~ 0
S7_QSPI_CS_N
Text HLabel 4850 5300 0 50 Input ~ 0
S7_RST_N
Wire Wire Line
4850 5300 5000 5300
Text HLabel 4850 5400 0 50 BiDi ~ 0
S7_INIT_B
Wire Wire Line
4850 5400 5000 5400
Text HLabel 4850 5500 0 50 Output ~ 0
S7_DONE
Wire Wire Line
4850 5500 5000 5500
Text Label 6350 1750 0 50 ~ 0
P6_UART_TX
Text Label 6350 1850 0 50 ~ 0
P6_UART_RX
Text Label 6350 1950 0 50 ~ 0
P7_UART_TX
Text Label 6350 2050 0 50 ~ 0
P7_UART_RX
Text Label 6350 2150 0 50 ~ 0
P8_UART_TX
Text Label 6350 2250 0 50 ~ 0
P8_UART_RX
Text Label 6350 2350 0 50 ~ 0
P9_UART_TX
Text Label 6350 2450 0 50 ~ 0
P9_UART_RX
Text Label 6350 2550 0 50 ~ 0
P10_UART_TX
Text Label 6350 2650 0 50 ~ 0
P10_UART_RX
Text Label 6350 2750 0 50 ~ 0
P11_UART_TX
Text Label 6350 2850 0 50 ~ 0
P11_UART_RX
Text HLabel 3100 1350 0 50 Input ~ 0
12V0
Wire Wire Line
3100 1350 3200 1350
Text HLabel 3100 1450 0 50 Input ~ 0
3V3
Wire Wire Line
3100 1450 3200 1450
Text Label 3100 1550 2 50 ~ 0
GND
Wire Wire Line
3100 1550 3200 1550
Text HLabel 3150 3050 0 50 BiDi ~ 0
I2C_SDA
Wire Wire Line
3150 3050 3200 3050
Text HLabel 3150 3150 0 50 Input ~ 0
I2C_SCL
Wire Wire Line
3150 3150 3200 3150
Text HLabel 6600 3350 2 50 Input ~ 0
EXT_TRIG_1_P
Text HLabel 6600 3450 2 50 Input ~ 0
EXT_TRIG_1_N
Wire Wire Line
6600 3350 6350 3350
Wire Wire Line
6350 3450 6600 3450
Text HLabel 6600 3650 2 50 Input ~ 0
LA_REFCLK_P
Wire Wire Line
6600 3650 6350 3650
Text HLabel 6600 3750 2 50 Input ~ 0
LA_REFCLK_N
Wire Wire Line
6600 3750 6350 3750
Text HLabel 6600 3950 2 50 Input ~ 0
SYNC_CLK_1_P
Wire Wire Line
6600 3950 6350 3950
Text HLabel 6600 4050 2 50 Input ~ 0
SYNC_CLK_1_N
Wire Wire Line
6600 4050 6350 4050
Text HLabel 6600 4250 2 50 Output ~ 0
TRIG_OUT_P
Wire Wire Line
6600 4250 6350 4250
Text HLabel 6600 4350 2 50 Output ~ 0
TRIG_OUT_N
Wire Wire Line
6600 4350 6350 4350
NoConn ~ 9100 4850
NoConn ~ 9100 4950
NoConn ~ 9100 5050
NoConn ~ 9100 5150
NoConn ~ 9100 5250
NoConn ~ 9100 5350
NoConn ~ 9100 5450
NoConn ~ 9100 5550
NoConn ~ 9100 5650
NoConn ~ 9100 5750
NoConn ~ 9100 850
NoConn ~ 9100 4450
NoConn ~ 9100 4550
NoConn ~ 9100 4650
NoConn ~ 9100 4750
Text HLabel 5000 4250 0 50 Output ~ 0
GTX_TRIG_OUT_P
Text HLabel 5000 4350 0 50 Output ~ 0
GTX_TRIG_OUT_N
$EndSCHEMATC
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