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revC2 #196
revC2 #196
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@marcan I did the layout for the new ADC. In my layout the new TVS diodes for the ADC (needed to keep the 36 Vmax capability of the ADC) aren't symmetric: Is that ok with you or do you have a better idea how to place them? I wanted to put them as near to the Vsense inputs as possible as this helps against ESD. |
The main reason to remove the ground pads is assembly reliability. In previous boards it was observed that it is fairly easy to create shorts between the ground pads and signal pads of the package.
The previous footprint was causing the solder stop webbing to be very thin which can result in the webbing missing on PCBs and result in shorts during reflow.
The datasheet has a finer footprint with smaller pads and smaller Via drills.
This change seems like a big diff but it only really changes SOIC-8 and MSOP-8. They mostly bring roundrect changes and increase pad length for better fileting.
* The 8x resistor arrays are not as common as 4x. Thus the 8x end up being more expensive and harder to source. * The SOT-563 package has slightly harder to solder than the SOT-363. Also the level shifter in SOT-363 is lower cost.
All footprints that are still not roundrect in the official KiCad library moved to local Glasgow footprint library and updated to roundrect pads. Also made a version of the 2x22 pin 1.27mm pitch LVDS connector with alignment pins. This will allow us to have accurate enough position of the connector so we can reliably connect to it in the pogopin tester and to possible daugter boards.
As part of rerouting also moved half of the power via under the packages. We regained some space thanks to that resulting in slightly cleaner routing.
All part IDs and values are now meant to be printed on the Fab layer as hardcopy manual assembly and population guide. The space on the silkscreen used for part IDs was partly traded against logical circuit block documentation. This is just the first pass and meant as a stepping stone. The goal is to have the logical functionality be as self descriptive on the silkscreen as possible.
Mainly improved readability of the Pull-Up/-Down control block legend. This resulted in some of the passives being moved out of the way to make space for the legend. Also added legend that indicates which level shifter is responsible for which IO signal, including Sync.
They were not aligned in a vertical line. For aethetic reasons this is now fixed. :)
The GPIO extenders can set a Pull-Up/-Down resistor or do nothing. That is not the same thing as HiZ. HiZ is only true if the level shifters are also set to input. So P- (Pull nothing or Passive) is a better term.
This is the inital routing pass. This is the status after esden's Twitch stream on Tuesday May 26th 2020.
Replaced nono_hana with an outlive version and made the Serial Number box an outline. This will make the black silkscreen on white solder mask look "right". Should still work for light silk on dark solder stop.
It was decided to be DNP for poduction, but there are still regularly questions about it popping up. So better completely remove it.
schematics part of #165 done
Also add new footprints where necessary, fix a silkscreen bug Layout for new components still TODO
Add manufacturer names & MPNs, remove stray wire, uppercase R in resistor values
…rsion. After testing and playing around with the small SMD tact switch we came to the conclusion that a slightly bigger button will fit in the same space and will give us more options. Also the longer, bigger and lower weight tact switch will feel nicer and fit in the case better.
Also fixed up the silkscreen and fab layers.
…ane below voltage regulators
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I went through every commit and individually reviewed each one with a significant change up to this point. Things look very good (thanks @esden and @electroniceel for the work!)
Most of my questions were resolved on IRC; the only one I have left is the copper fill added in 25c3a51. That seems to me like it would not improve anchoring much, but would make the type-C connector extremely hard to rework.
@whitequark thank you for the review. I have used similar technique on another board and it worked fine. The thing to consider here is that the shield fill around the part is pretty small and does not connect to a larger ground plane that would act as a heat sink. So my assumption is that it is not a big problem when using a typical hot air rework station. It is necessary to use a hot air rework station due to the shield being soldered into the board in any case. That said it is a very good point you are making here. I will test and film how hard it is to rework the USB-C connectors on the Glasgow. Then we can make an educated decision about it. |
Sounds good! I missed the fact that it is not connected to a ground plane. Since it is not I agree that the impact on rework is much smaller than what I have thought it is. |
The reset button had to be TH. Logos should be virtual.
The footprint in the KiCad library works but it is too large and could cause assembly reliability issues. The new footprint and 3D model are based on the official Diodes Inc data and match the part we are using.
The outer pads of the resistor pack footprints were slightly too small. This can cause assembly reliability isues.
As recommended by KiCad this setting should only be used when explicitly asked by the PCB manufacturer. It depends on their needs and capabilities and is usually done as part of gerber file pre processing done by the PCB manufacturer.
Shouldn't this be merged? Seeing as we have revC2's manufactured and shipped already. |
I was waiting for you and @electroniceel to validate the design before I merge it. I did not want to make it seem like it is a "you can safely build this design for yourself" until you two had a chance to test things. If the new circuits are 100% confirmed to be working as intended, we can generate all the generated assets (gerber files and BOM) and then we can merge it. But if you rather have this in mainline already as is, I can rebase it and merge it if you want. |
I talked to @electroniceel and we decided to hold off merging, even though this will result in some "revC2"s floating around that are not actually revC2-as-merged... |
Here is the TODO list for me bore we can merge:
|
I've just built some of these boards. Nice work on the DFM changes @esden! If others make this mistake the parts do kind of fit, bit will require slight touch-up on the pins to ensure connectivity. |
Thanks @gregdavill for spotting & reporting this.
Oops. Sorry. Especially this package change was designed to make this board easier for others to make, we got several reports of the DRL package being difficult to work with. Unfortunately this made it even harder for you to get right. Thank you very much for reporting this, I just fixed it in the revC2 branch. |
This pull request is intended to track the work on the revC2 of the hardware.
Main goals of this revision compared to revC1 is to improve DFM (Design For Manufacture). This includes:
Secondary goal is improvement of the design based on user feedback:
Please refer to this pull request in issues that track change requests for revC2.
Do not merge yet. ;)