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Add design: VexRISC-V Linux LiteX SoC with LiteDRAM and LiteEth (50T) #152

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HackerFoo opened this issue Jun 16, 2020 · 7 comments
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Add design: VexRISC-V Linux LiteX SoC with LiteDRAM and LiteEth (50T) #152

HackerFoo opened this issue Jun 16, 2020 · 7 comments

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@HackerFoo
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@HackerFoo
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I think this is the baselitex design.

@HackerFoo HackerFoo added this to To do in fpga-tool-perf Jun 16, 2020
@HackerFoo HackerFoo moved this from To do to Done in fpga-tool-perf Jun 16, 2020
@tcal-x
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tcal-x commented Jun 16, 2020 •
edited by unfurl-links bot

@HackerFoo you've seen this, right?

https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/xc/xc7/tests/soc/litex/base

GitHub
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. - SymbiFlow/symbiflow-arch-defs

@HackerFoo HackerFoo moved this from Done to In progress in fpga-tool-perf Jun 16, 2020
@HackerFoo
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@tcal-x Yes, thanks.

@HackerFoo HackerFoo changed the title Add design: VexRISC-V Linux LiteX SoC with LiteDRAM and LiteEth Add design: VexRISC-V Linux LiteX SoC with LiteDRAM and LiteEth (50T) Jun 17, 2020
@acomodi
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acomodi commented Jun 17, 2020 •
edited

I believe this can actually be closed. This is indeed the baselitex project in FPGA tool perf.

fpga-tool-perf automation moved this from In progress to Done Jun 17, 2020
@mithro
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mithro commented Jun 17, 2020

Can we rename baselitex to litex-vexriscv-ddr or something? baselitex doesn't really mean much?

@HackerFoo
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The designs need documentation: #162

@HackerFoo
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I have the design building on Hydra as part of: #166

@kgugala kgugala removed this from Done in fpga-tool-perf Jan 17, 2022
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@mithro @HackerFoo @acomodi @tcal-x