Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) #153

Open
HackerFoo opened this issue Jun 16, 2020 · 1 comment
Open

Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) #153

HackerFoo opened this issue Jun 16, 2020 · 1 comment
Labels
designs Related to designs being used to evaluate the performance in the FPGA Tool Perf enhancement New feature or request

Comments

@HackerFoo
Copy link
Contributor

No description provided.

@HackerFoo HackerFoo added this to To do in fpga-tool-perf Jun 16, 2020
@HackerFoo HackerFoo changed the title Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth Add design: Rocket Linux LiteX SoC with LiteDRAM and LiteEth (50T) Jun 17, 2020
@acomodi acomodi moved this from To do to Low Priority in fpga-tool-perf Jun 17, 2020
@HackerFoo HackerFoo moved this from Test coverage to Flow in fpga-tool-perf Jun 17, 2020
@HackerFoo
Copy link
Contributor Author

Related issue: timvideos/litex-buildenv#466

@HackerFoo HackerFoo self-assigned this Jun 23, 2020
@HackerFoo HackerFoo moved this from Not Started to In progress in fpga-tool-perf Jun 23, 2020
@mithro mithro added enhancement New feature or request designs Related to designs being used to evaluate the performance in the FPGA Tool Perf labels Jun 25, 2020
pawelsag pushed a commit to antmicro/fpga-tool-perf that referenced this issue May 28, 2021
@imphil
Veriblelint: Support waivers
e84cc39 
Since chipsalliance/verible#293 Verible lint supports
(multiple) waiver files; add support for that to edalize.

I didn't add any version detection for Verible since we're currently
assuming `master` of Verible for edalize, as long as Verible hasn't done
a stable release yet.

Fixes chipsalliance#153
@HackerFoo HackerFoo removed their assignment Jun 23, 2021
@kgugala kgugala removed this from In progress in fpga-tool-perf Jan 17, 2022
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
designs Related to designs being used to evaluate the performance in the FPGA Tool Perf enhancement New feature or request
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@mithro @HackerFoo