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Add support for SDC constraint propagation through clock primitives #18

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tmichalak opened this issue Jun 16, 2020 · 1 comment
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Add support for SDC constraint propagation through clock primitives #18

tmichalak opened this issue Jun 16, 2020 · 1 comment

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@tmichalak
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SDC information should be imported into Yosys from XDC and attached to the right entities.
Next the information should propagate across PLL, BUF, MCMM primitives.
Finally, the SDC information should be exported from Yosys in form of an SDC file.
@mithro mithro mentioned this issue Sep 14, 2020
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@tmichalak
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Initial support for Natural, Buffer and Clock Divider propagation has been implemented in PRs #27 and #37.

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@tmichalak