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Re-running a test gives incorrect timing results #155

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HackerFoo opened this issue Jun 17, 2020 · 0 comments

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bug

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HackerFoo commented Jun 17, 2020

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HackerFoo added this to To do in fpga-tool-perf

acomodi moved this from To do to High Priority in fpga-tool-perf

HackerFoo mentioned this issue

Build a nix expression to allow running tests with different versions of Yosys #166

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mithro added the bug label

pawelsag pushed a commit to antmicro/fpga-tool-perf that referenced this issue


          templates: yosys-makefile.j2: add missing edif file in clean rule (ch…

70dbd9b

…ipsalliance#155)

* templates: yosys-makefile.j2: add missing edif file in clean rule

* update reference files according to previous commit

kgugala removed this from Not Started in fpga-tool-perf

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