You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This affects PLL phase parameters. Instead of eg. 90.0 it has to be specified as 90000. This makes eg. LiteX generated verilog files not work.
We need to create an XDC plugin that will perform the required computations and set the values on the required parameters, which end up in eblif, instead of having to add some verilog functions during techmap translation.
Xilinx describes the dynamic reconfiguration in PLLs and MMCMs in a document
The text was updated successfully, but these errors were encountered:
For now the necessary calculations will be performed in TCL. A plugin with the getparam command has been implemented which together with the existing setparam can be used to manipulate the required parameter values before techmapping. The integration is part of an arch-defs issue
This affects PLL phase parameters. Instead of eg. 90.0 it has to be specified as 90000. This makes eg. LiteX generated verilog files not work.
We need to create an XDC plugin that will perform the required computations and set the values on the required parameters, which end up in eblif, instead of having to add some verilog functions during techmap translation.
Xilinx describes the dynamic reconfiguration in PLLs and MMCMs in a document
The text was updated successfully, but these errors were encountered: