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base repository: azonenberg/starshipraider
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head repository: azonenberg/starshipraider
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compare: c27534c4ae09
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on May 2, 2020

  1. Copy the full SHA
    c27534c View commit details
Showing with 283 additions and 11 deletions.
  1. +282 −10 rtl/BLONDEL/blondel.srcs/sources_1/new/AcquisitionManager.sv
  2. +1 −1 rtl/antikernel-ipcores
292 changes: 282 additions & 10 deletions rtl/BLONDEL/blondel.srcs/sources_1/new/AcquisitionManager.sv
Original file line number Diff line number Diff line change
@@ -54,15 +54,217 @@ module AcquisitionManager(
output logic TCPv4TxBus tcp_tx_bus
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Trigger logic

logic trigger_found = 0;
logic[2:0] trigger_pos = 0;
logic[7:0] last_sample = 0;

always_ff @(posedge adc_clk) begin

//Assume no trigger found by default
trigger_found <= 0;
last_sample <= adc_bus.samples[0];

//Search from sample 0 (newest) to 7 (oldest)
//so we return the first trigger if there is one.
//For now, hard code rising edge trigger at the 50% level
for(integer i=0; i<8; i=i+1) begin

//Special case oldest sample
if(i == 7) begin
if( (adc_bus.samples[i] >= 128) && (last_sample < 128) ) begin
trigger_found <= 1;
trigger_pos <= i;
end
end

//Nope, normal
else begin
if( (adc_bus.samples[i] >= 128) && (adc_bus.samples[i+1] < 128) ) begin
trigger_found <= 1;
trigger_pos <= i;
end
end

end

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Waveform data buffer

logic ram_wr_en = 0;
logic[10:0] ram_wr_addr = 0;
h1520bus_t ram_wr_data = 0;

logic ram_rd_en = 0;
logic[10:0] ram_rd_addr = 0;
h1520bus_t ram_rd_data;

MemoryMacro #(
.WIDTH(64), //8 samples * 8 bits
.DEPTH(2048), //2K words = 16K samples
.USE_BLOCK(1),
.OUT_REG(1),
.DUAL_PORT(1),
.TRUE_DUAL(1)
) waveform_buffer (
.porta_clk(adc_clk),
.porta_en(ram_wr_en),
.porta_addr(ram_wr_addr),
.porta_we(ram_wr_en),
.porta_din(ram_wr_data),
.porta_dout(),

.portb_clk(tcp_clk),
.portb_en(ram_rd_en),
.portb_addr(ram_rd_addr),
.portb_we(1'b0),
.portb_din(),
.portb_dout(ram_rd_data)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// ADC buffering logic

wire trigger_arm_sync;
logic waveform_ready = 0;

enum logic[3:0]
{
ADC_STATE_IDLE = 0,
ADC_STATE_PRE_TRIG = 1,
ADC_STATE_ARMED = 2,
ADC_STATE_CAPTURE = 3,
ADC_STATE_DONE = 4
} adc_state = ADC_STATE_IDLE;

logic[10:0] trigger_addr = 0;
logic[2:0] trigger_phase = 0;

always_ff @(posedge adc_clk) begin

ram_wr_en <= 0;
waveform_ready <= 0;

case(adc_state)

ADC_STATE_IDLE: begin

//When we get the arm pulse, start collecting pre-trigger data
if(trigger_arm_sync) begin
ram_wr_addr <= 0;
adc_state <= ADC_STATE_PRE_TRIG;
end

end //end ADC_STATE_IDLE

ADC_STATE_PRE_TRIG: begin

ram_wr_en <= 1;
ram_wr_addr <= ram_wr_addr + 1;
ram_wr_data <= adc_bus;

if(ram_wr_addr == 1024)
adc_state <= ADC_STATE_ARMED;

end //end ADC_STATE_PRE_TRIG

ADC_STATE_ARMED: begin

ram_wr_en <= 1;
ram_wr_addr <= ram_wr_addr + 1;
ram_wr_data <= adc_bus;

if(trigger_found) begin
trigger_phase <= trigger_pos;
trigger_addr <= ram_wr_addr + 1;
adc_state <= ADC_STATE_CAPTURE;
end

end //end ADC_STATE_ARMED

ADC_STATE_CAPTURE: begin

//Done?
if( (ram_wr_addr + 1) == trigger_addr) begin
adc_state <= ADC_STATE_DONE;
waveform_ready <= 1;
end

//Nope
else begin
ram_wr_en <= 1;
ram_wr_addr <= ram_wr_addr + 1;
ram_wr_data <= adc_bus;
end

end //end ADC_STATE_CAPTURE

ADC_STATE_DONE: begin
//stay here until reset
end //end ADC_STATE_DONE

endcase

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Event clock domain crossing

wire waveform_ready_sync;

PulseSynchronizer sync_waveform_ready(
.clk_a(adc_clk),
.pulse_a(waveform_ready),
.clk_b(tcp_clk),
.pulse_b(waveform_ready_sync)
);

logic trigger_arm = 0;

PulseSynchronizer sync_arm(
.clk_a(tcp_clk),
.pulse_a(trigger_arm),
.clk_b(adc_clk),
.pulse_b(trigger_arm_sync)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TCP receive path

/*
enum logic[1:0]
{
RX_STATE_IDLE = 0
} rx_state = RX_STATE_IDLE;
always_ff @(posedge tcp_clk) begin
RX_STATE_IDLE: begin
end //end RX_STATE_IDLE
end
*/

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TCP transmit path (TODO: refactor some of this out into a separate arbiter)

enum logic[3:0]
{
TX_STATE_IDLE = 0,
TX_STATE_UART = 1
TX_STATE_IDLE = 0,
TX_STATE_UART = 1,
TX_STATE_WAVEFORM_0 = 2,
TX_STATE_WAVEFORM_1 = 3,
TX_STATE_WAVEFORM_2 = 4
} tx_state = TX_STATE_IDLE;

logic waveform_pending = 0;
logic tx_phase = 0;

always_ff @(posedge tcp_clk) begin

uart_cts <= 0;
@@ -71,14 +273,39 @@ module AcquisitionManager(
tcp_tx_bus.commit <= 0;
tcp_tx_bus.drop <= 0;

trigger_arm <= 0;

ram_rd_en <= 0;

if(waveform_ready_sync)
waveform_pending <= 1;

//If we get a byte on the incoming TCP connection, arm the trigger
if(tcp_rx_bus.commit && (tcp_rx_bus.dst_port == tcp_port) ) begin
trigger_arm <= 1;

tcp_tx_bus.dst_port <= tcp_rx_bus.src_port;
tcp_tx_bus.src_port <= tcp_port;
tcp_tx_bus.dst_ip <= tcp_rx_bus.src_ip;
tcp_tx_bus.sockid <= tcp_rx_bus.sockid;
end

case(tx_state)

////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Wait for data to transmit

TX_STATE_IDLE: begin

if(uart_rts) begin
if(waveform_pending) begin
waveform_pending <= 0;
ram_rd_en <= 1;
ram_rd_addr <= 0;
tx_phase <= 0;
tx_state <= TX_STATE_WAVEFORM_0;
end

else if(uart_rts) begin
uart_cts <= 1;
tx_state <= TX_STATE_UART;
end
@@ -97,7 +324,47 @@ module AcquisitionManager(
end //end TX_STATE_UART

////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TODO: actual waveform transmit path
// Actual waveform transmit path

TX_STATE_WAVEFORM_0: begin

tcp_tx_bus.start <= 1;
tx_state <= TX_STATE_WAVEFORM_1;

end //end TX_STATE_WAVEFORM_0

TX_STATE_WAVEFORM_1: begin

//Send the data
tcp_tx_bus.data_valid <= 1;
tcp_tx_bus.bytes_valid <= 4;

tx_phase <= !tx_phase;

//First half (start reading more data)
if(tx_phase == 0) begin
tcp_tx_bus.data <= ram_rd_data.samples[7:4];

ram_rd_en <= 1;
ram_rd_addr <= ram_rd_addr + 1;
end

else begin
tcp_tx_bus.data <= ram_rd_data.samples[3:0];

//For now, stop after the first 128 rows (1024 samples)
//(note that we alreasy incremented ram_rd_addr)
if(ram_rd_addr == 128)
tx_state <= TX_STATE_WAVEFORM_2;

end

end //end TX_STATE_WAVEFORM_1

TX_STATE_WAVEFORM_2: begin
tcp_tx_bus.commit <= 1;
tx_state <= TX_STATE_IDLE;
end //end TX_STATE_WAVEFORM_2

endcase

@@ -108,13 +375,18 @@ module AcquisitionManager(

ila_0 ila(
.clk(tcp_clk),
.probe0(uart_rts),
.probe1(uart_cts),
.probe2(uart_tx_bus.start),
.probe3(uart_tx_bus.commit),
.probe0(trigger_arm),
.probe1(waveform_ready_sync),
.probe2(tx_state),
.probe3(waveform_pending),
.probe4(tcp_tx_bus.start),
.probe5(tcp_tx_bus.commit),
.probe6(tx_state)
.probe5(ram_rd_en),
.probe6(ram_rd_addr),
.probe7(tx_phase),
.probe8(ram_rd_data),
.probe9(tcp_tx_bus.data_valid),
.probe10(tcp_tx_bus.data),
.probe11(tcp_tx_bus.commit)
);

endmodule
2 changes: 1 addition & 1 deletion rtl/antikernel-ipcores