serial: A proposal to add verification using formal tools #4
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- RX now enters DONE state 1 clock earlier to avoid delay - RX now checks for one more bit (taking (divisor+1)-long time span) while making the received data ready for collection
* `TX.continuous` is an externally driven Signal, resets to 0 (deasserted) * When asserted, TX assumes that `TX.data` is valid AT THE SAME TIME when the start bit starts to be sent out * When deasserted, TX assumes that `TX.data` is valid BEFORE the start bit is sent, and AT THE SAME TIME when `TX.ack` is asserted
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* This FV case now inserts any delay (0 - divisor+1) between the final bit and the start bit (0) of the next sequence.
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On this pull request, I propose modifications on @whitequark's UART / asynchronous serial transmitter/receiver that would introduce a way to formally verify the I/O. The major changes include:
AsyncSerialRXnow has the following signals:ackfor enabling transfer of received data to another module,busyfor indicating ongoing data reception, andr_rdyfor indicating whether or not the received data is ready to transfer.AsyncSerialTXnow has the following signals:ackfor enabling transmission of data from another module,busyfor indicating ongoing data transmission, andw_donefor indicating whether or not the data has been transmitted.AsyncSerialLoopbackTestCaseandAsyncSerialBitstreamTestCase) that use a formal verification approach has been added tonmigen_stdio.test.test_serial. In short, they use Bounded Model Checking to check if the desired states (e.g. "DONE" for correct data transmission, or "ERROR" for data with errors) can be reached within certain numbers of cycles, usually equal to the duration that starts before the RX/TX is enabled and ends after the RX/TX assertsr_rdy/w_done.I will provide further useful descriptions and explanations later on. I look forward to seeing further comments, thanks.
Edit: the version check in
setup.pywill be modified according to the final decision.