-
Notifications
You must be signed in to change notification settings - Fork 1
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
serial: A proposal to add verification using formal tools #4
Open
ghost
wants to merge
12
commits into
m-labs:serial
Choose a base branch
from
HarryMakes:serial
base: serial
Could not load branches
Branch not found: {{ refName }}
Loading
Could not load tags
Nothing to show
Loading
Are you sure you want to change the base?
Some commits from the old base branch may be removed from the timeline,
and old review comments may become outdated.
+761
−79
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
- RX now enters DONE state 1 clock earlier to avoid delay - RX now checks for one more bit (taking (divisor+1)-long time span) while making the received data ready for collection
* `TX.continuous` is an externally driven Signal, resets to 0 (deasserted) * When asserted, TX assumes that `TX.data` is valid AT THE SAME TIME when the start bit starts to be sent out * When deasserted, TX assumes that `TX.data` is valid BEFORE the start bit is sent, and AT THE SAME TIME when `TX.ack` is asserted
bab3676
to
5e2f086
Compare
fe7c4df
to
f64d8d7
Compare
* This FV case now inserts any delay (0 - divisor+1) between the final bit and the start bit (0) of the next sequence.
From 46dac6a: the |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
On this pull request, I propose modifications on @whitequark's UART / asynchronous serial transmitter/receiver that would introduce a way to formally verify the I/O. The major changes include:
AsyncSerialRX
now has the following signals:ack
for enabling transfer of received data to another module,busy
for indicating ongoing data reception, andr_rdy
for indicating whether or not the received data is ready to transfer.AsyncSerialTX
now has the following signals:ack
for enabling transmission of data from another module,busy
for indicating ongoing data transmission, andw_done
for indicating whether or not the data has been transmitted.AsyncSerialLoopbackTestCase
andAsyncSerialBitstreamTestCase
) that use a formal verification approach has been added tonmigen_stdio.test.test_serial
. In short, they use Bounded Model Checking to check if the desired states (e.g. "DONE" for correct data transmission, or "ERROR" for data with errors) can be reached within certain numbers of cycles, usually equal to the duration that starts before the RX/TX is enabled and ends after the RX/TX assertsr_rdy
/w_done
.I will provide further useful descriptions and explanations later on. I look forward to seeing further comments, thanks.
Edit: the version check in
setup.py
will be modified according to the final decision.