@acomodi FYI

@mkurc-ant can you please create a smaller failing test case in xc7/tests/serdes? This behavior is typical, I'm surprised it wasn't caught earlier.

For both @mkurc-ant and @acomodi reference, all input pins are connected to <const1> when no bits are set in the bitstream. Inverters are typically set such when the invert feature is not set, the hardware is disabled. As a concrete example, the enable port of the BUFGCTRL defaults to <const0> because the inverter on the control line defaults to being enabled. So the default routing fabric routes a <const1> to the inverter, the inverter inverts by default, resulting in a <const0> being sent to the enable line, disabling the hardware.

To be clear, when I say "inverter feature", I'm refering to a feature that sets bits. For the reasons above, some inverter features disable the inverter, to achieve the above behavior.

Does that make sense?

@litghost Yes, all of that makes sense to me.

My findings that I described in this issue are based on a problem encountered with fasm2bels ran on the LiteX with DDR design. When eg. all T inputs of an OSERDES are connected to 0 (explicitly) they are routed to <const 0> by SymbiFlow with inverters disabled. However, when importing design decoded by fasm2bels to Vivado it complains about routing conflict. Vivado expects all those inputs to be routed to <const 1> and have inverters enabled.

I have a tiny test that I synthesized with Vivado and observed how the routing + inverters behave. I can port it to use with SymbiFlow.

@litghost Yes, all of that makes sense to me.

My findings that I described in this issue are based on a problem encountered with fasm2bels ran on the LiteX with DDR design. When eg. all T inputs of an OSERDES are connected to 0 (explicitly) they are routed to <const 0> by SymbiFlow with inverters disabled. However, when importing design decoded by fasm2bels to Vivado it complains about routing conflict. Vivado expects all those inputs to be routed to <const 1> and have inverters enabled.

I have a tiny test that I synthesized with Vivado and observed how the routing + inverters behave. I can port it to use with SymbiFlow.

That pattern is common in the 7-series fabric. Take a look at the bram techmap, it has logic to handle exactly what you are describing.

I've added a test demonstrating this issue: #1261