Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

serial: fixes, more tests and docstrings. #3

Open
wants to merge 7 commits into
base: serial
Choose a base branch
from
Open

serial: fixes, more tests and docstrings. #3

wants to merge 7 commits into from

Conversation

jfng
Copy link

@jfng jfng commented Jan 1, 2020

No description provided.

from nmigen.back.pysim import *
from nmigen.test.utils import *
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This module is not called _test because (I think) otherwise test runners would get confused. Nevertheless it is not a part of public API.

Jean-François Nguyen added 3 commits January 3, 2020 10:44
This is a best-effort attempt. The clock divisor signal can still be set to an
invalid value during operation.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

2 participants