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Incorrect PLL IN_USE feature #1141
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IN_USE:
versus
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Looks like |
That's strange. I've runned both Investigating... |
The solution for Please provide SHA of the prjxray-db you are using and if possible SHA of the prjxray repo used to generate it. |
Even though this does not regard the bits collision issue, I have seen that, by driving the PLL directly from the IBUF_clk net lets the Instead, if the CLKIN comes from a BUFG, VPR chooses a different path, avoiding the generation of this failure. |
@acomodi By "IBUF" you mean a regular input buffer, not the dedicated clock input buffer? Because we do not have bits for clock input buffers that are in HCLK_IOI3 tile. Could you elaborate what is the failure? |
The failure is the one related to this issue: if the As regards the IBUF clk net, i mean the dedicated clock input buffer (the W5 IOPAD). |
f4pga/prjxray-db@ca781e7 : https://github.com/SymbiFlow/prjxray-db/blob/master/artix7/segbits_cmt_top_l_upper_t.db#L74 |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
prjxray master is still showing |
Ok, I'm going to run a full build of the db locally (clean build, different machine) and see where the problem is. |
f4pga/f4pga-arch-defs#1150 failed as a result of a bad segbit definition:
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