from nmigen import *
from nmigen.asserts import *
from nmigen.cli import main


class A(Elaboratable):
    def __init__(self):
        a = [1, 2, 3, 4, 5, 6]
        self.addr = Signal.range(0, len(a))
        self.data = Signal(8)
        self.mem = Memory(width=8, depth=len(a), init=a)

    def elaborate(self, platform):
        m = Module()
        m.submodules.rdport = rdport = self.mem.read_port()
        m.d.comb += [
            rdport.addr.eq(self.addr),
            self.data.eq(rdport.data),
        ]
        return m


if __name__ == "__main__":
    m = Module()
    a = A()
    m.submodules.a = a

    m.d.comb += Cover(a.addr == 0)

    main(m, ports=[a.addr, a.data])