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base repository: m-labs/nmigen
base: 376180f21e9a
head repository: m-labs/nmigen
compare: c8e6ec2ac703
Commits on Aug 21, 2019
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vendor.xilinx_series7: use STARTUPE2, not STARTUPE3.
STARTUPE3 is for Ultrascale.
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Commits on Aug 22, 2019
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back.rtlil: add support for real (float) parameters on Instances.
Required for Xilinx MMCME2_BASE, etc.
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back.rtlil: print real parameters with maximum precision.
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vendor.lattice_ecp5: add Diamond support.
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Commits on Aug 23, 2019
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build.run: add BuildPlan.digest(), useful for caching.
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back.pysim: don't crash when trying to drive a nonexistent domain clock.
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back.pysim: implement sim.add_clock(if_exists=True).
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Commits on Aug 25, 2019
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vendor.lattice_ecp5: revert default toolchain to Trellis.
This was unintentionally changed in 7fc1058.
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Commits on Aug 26, 2019
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Commits on Aug 28, 2019
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_toolchain: new module, for injecting dependencies in e.g. Nix.
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Commits on Aug 30, 2019
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build.dsl: allow both str and int resource attributes.
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vendor.lattice_ecp5: drive GSR synchronous to user clock by default.
Fixes #167.
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Commits on Aug 31, 2019
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Commits on Sep 3, 2019
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Commits on Sep 6, 2019
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setup: replace versioneer with setuptools_scm.
Has the same problems with git-archive but is much less invasive.
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Remove nmigen.lib from prelude.
Currently it's just MultiReg, and there's no particularly good reason to privilege this specific CDC primitive so much.
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Commits on Sep 8, 2019
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hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).
Fixes #196.
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hdl.mem,lib,examples: use Signal.range().
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hdl.dsl: add Default(), an alias for Case() with no arguments.
Fixes #197.
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Commits on Sep 10, 2019
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Commits on Sep 11, 2019
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back: return name map from convert_fragment().
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build.plat,vendor: allow clock constraints on arbitrary signals.
Currently only done for Synopsys based toolchains (i.e. not nextpnr). Refs #88.
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Commits on Sep 12, 2019
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lib.cdc: adjust MultiReg for new CDC primitive conventions.
Refs #97.
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lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
Refs #97.
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lib.cdc: make domain properties private.
It is not correct to access domain properties from user code, because it will not match the reality if DomainRenamer has been applied to the module.
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README: update Yosys version requirement.
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lib.fifo: remove SyncFIFO.replace.
This obscure functionality was likely only ever used in old MiSoC code, and doesn't justify the added complexity. It was also not provided (and could not be reasonably provided) in SyncFIFOBuffered, which made its utility extremely marginal.
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lib.fifo: make fwft a keyword-only argument.
Because it accepts a boolean.
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hdl.mem: use keyword-only arguments as appropriate.
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vendor.xilinx_7series: Vivado requires bash on *nix as well.
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build.plat: bypass tool detection if NMIGEN_*_env is set.
It's not practical to detect tools within the toolchain environment for various reasons, so just assume the tools are there if the user says they are. Before this commit, the tools would be searched outside the toolchain environment, which of course would always fail for Vivado, ISE, etc.
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Commits on Sep 13, 2019
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lib.fifo: adjust properties to have consistent naming.
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hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
Refs #147.
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Commits on Sep 14, 2019
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hdl.dsl: improve error messages for Case().
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hdl.ast: add Value.matches(), accepting same language as Case().
Fixes #202.
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Commits on Sep 16, 2019
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hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum pat…
…terns. Fixes #207.
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Commits on Sep 20, 2019
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back.pysim: fix simulation of Value.xor().
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