(Verilog) nMigen should provide better information about original source code locations #293
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If you are using SymbiYosys, do not emit Verilog from nMigen. Instead, emit RTLIL from nMigen, which already has far more precise location information than Verilog |
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Doesn't it only works with yosys and its friends? I had not only it in mind, but also vendor specific tools which support verilog and preprocessor directives. |
Correct.
There is little nMigen can do directly here, since it relies on Yosys to emit Verilog. It is possible to improve the Yosys Verilog backend to emit |
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Consider for example this report from yosys
If I go there, I'll see
and I'll have to jump to
\$cover$check, maybe even further to variables like\$157.Instead nMigen should generate
In other words
a) source location should be generated next to cover/assert statements, not just next to their corresponding variable
b) Instead of comments like
(* src = "/mnt/e/abc/cde.py:17" *), source locations should be generated with `line so tools like SymbiYosys can point the right location (maybe optionally: verilog95 doesn't describe `line directive, it was added in verilog 2001)The text was updated successfully, but these errors were encountered: