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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: d139f340b33c
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Oct 2, 2019

  1. back.rtlil: don't cache wires for legalized switch tests.

    This causes miscompilation of code such as:
    
      r = Array([self.a, self.b])
      m = Module()
      with m.If(r[self.s]):
          m.d.comb += self.o.eq(1)
      return m
    whitequark committed Oct 2, 2019
    Copy the full SHA
    d139f34 View commit details
Showing with 11 additions and 3 deletions.
  1. +11 −3 nmigen/back/rtlil.py
14 changes: 11 additions & 3 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -681,9 +681,17 @@ def on_property(self, stmt):
def on_Switch(self, stmt):
self._check_rhs(stmt.test)

if stmt not in self._test_cache:
self._test_cache[stmt] = self.rhs_compiler(stmt.test)
test_sigspec = self._test_cache[stmt]
if not self.state.expansions:
# We repeatedly translate the same switches over and over (see the LHSGroupAnalyzer
# related code below), and translating the switch test only once helps readability.
if stmt not in self._test_cache:
self._test_cache[stmt] = self.rhs_compiler(stmt.test)
test_sigspec = self._test_cache[stmt]
else:
# However, if the switch test contains an illegal value, then it may not be cached
# (since the illegal value will be repeatedly replaced with different constants), so
# don't cache anything in that case.
test_sigspec = self.rhs_compiler(stmt.test)

with self._case.switch(test_sigspec, src=src(stmt.src_loc)) as switch:
for values, stmts in stmt.cases.items():