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base repository: m-labs/nmigen
base: d3f7cc8ed2a8
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head repository: m-labs/nmigen
compare: d139f340b33c
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Oct 2, 2019

  1. back.rtlil: don't cache wires for legalized switch tests. 

    This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
    whitequark committed Oct 2, 2019
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    d139f34 View commit details
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