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Original file line number | Diff line number | Diff line change |
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@@ -142,7 +142,7 @@ def _add_ff(self, m, xdr, src, dest, clk, kind): | |
i_prn=1, | ||
o_q=dest | ||
) | ||
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# Despite the altiobuf manual saying ENABLE_BUS_HOLD is optional, Quartus requires it to be specified. | ||
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def get_input(self, pin, port, attrs, invert): | ||
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@@ -318,19 +318,56 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert): | |
pin.i.attrs["useioff"] = "1" | ||
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for bit in range(pin.width): | ||
clk = pin.i_clk if pin.xdr != 0 else None | ||
if pin.xdr <= 1: | ||
clk = pin.i_clk if pin.xdr != 0 else None | ||
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self._add_ff(m, pin.xdr, self._invert_if(invert, ff_i[bit]), pin.i[bit], clk, "i") | ||
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m.submodules["{}_buf_{}".format(pin.name, bit)] = Instance("altiobuf_in", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=p_port[bit], | ||
i_datain_b=n_port[bit], | ||
o_dataout=ff_i[bit] | ||
) | ||
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self._add_ff(m, pin.xdr, self._invert_if(invert, ff_i[bit]), pin.i[bit], clk, "i") | ||
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m.submodules["{}_buf_{}".format(pin.name, bit)] = Instance("altiobuf_in", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=p_port[bit], | ||
i_datain_b=n_port[bit], | ||
o_dataout=ff_i[bit] | ||
) | ||
else: | ||
p_posedge = Signal() | ||
p_negedge = Signal() | ||
n_posedge = Signal() | ||
n_negedge = Signal() | ||
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m.submodules["{}_ddr_p_{}".format(pin.name, bit)] = Instance("altddio_in", | ||
p_width=1, | ||
i_datain=p_port[bit], | ||
i_inclock=pin.i_clk, | ||
o_dataout_h=p_posedge, | ||
o_dataout_l=p_negedge, | ||
) | ||
m.submodules["{}_ddr_n_{}".format(pin.name, bit)] = Instance("altddio_in", | ||
p_width=1, | ||
i_datain=n_port[bit], | ||
i_inclock=pin.i_clk, | ||
o_dataout_h=n_posedge, | ||
o_dataout_l=n_negedge, | ||
) | ||
m.submodules["{}_buf_p_{}".format(pin.name, bit)] = Instance("altiobuf_in", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=p_posedge, | ||
i_datain_b=n_posedge, | ||
o_dataout=self._invert_if(pin.i0[bit]) | ||
) | ||
m.submodules["{}_buf_n_{}".format(pin.name, bit)] = Instance("altiobuf_in", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=p_negedge, | ||
i_datain_b=n_negedge, | ||
o_dataout=self._invert_if(pin.i1[bit]) | ||
) | ||
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return m | ||
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def get_diff_output(self, pin, p_port, n_port, attrs, invert): | ||
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@@ -344,18 +381,55 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert): | |
pin.o.attrs["useioff"] = "1" | ||
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for bit in range(pin.width): | ||
clk = pin.o_clk if pin.xdr != 0 else None | ||
if pin.xdr <= 1: | ||
clk = pin.o_clk if pin.xdr != 0 else None | ||
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self._add_ff(m, pin.xdr, self._invert_if(invert, pin.o[bit]), ff_o[bit], pin.o_clk, "o") | ||
self._add_ff(m, pin.xdr, self._invert_if(invert, pin.o[bit]), ff_o[bit], pin.o_clk, "o") | ||
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m.submodules["{}_buf_{}".format(pin.name, bit)] = Instance("altiobuf_out", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=ff_o[bit], | ||
o_dataout=p_port[bit], | ||
o_dataout_b=n_port[bit] | ||
) | ||
m.submodules["{}_buf_{}".format(pin.name, bit)] = Instance("altiobuf_out", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=ff_o[bit], | ||
o_dataout=p_port[bit], | ||
o_dataout_b=n_port[bit] | ||
) | ||
else: | ||
p_posedge = Signal() | ||
p_negedge = Signal() | ||
n_posedge = Signal() | ||
n_negedge = Signal() | ||
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m.submodules["{}_ddr_p_{}".format(pin.name, bit)] = Instance("altddio_out", | ||
p_width=1, | ||
i_datain_h=p_posedge, | ||
i_datain_l=p_negedge, | ||
i_outclock=pin.o_clk, | ||
o_dataout=p_port[bit], | ||
) | ||
m.submodules["{}_ddr_n_{}".format(pin.name, bit)] = Instance("altddio_out", | ||
p_width=1, | ||
i_datain_h=n_posedge, | ||
i_datain_l=n_negedge, | ||
i_outclock=pin.o_clk, | ||
o_dataout=n_port[bit], | ||
) | ||
m.submodules["{}_buf_p_{}".format(pin.name, bit)] = Instance("altiobuf_out", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=self._invert_if(invert, pin.o0[bit]), | ||
o_dataout=p_posedge, | ||
o_dataout_b=n_posedge, | ||
) | ||
m.submodules["{}_buf_n_{}".format(pin.name, bit)] = Instance("altiobuf_out", | ||
p_NUMBER_OF_CHANNELS=1, | ||
p_ENABLE_BUS_HOLD="FALSE", | ||
p_USE_DIFFERENTIAL_MODE="TRUE", | ||
i_datain=self._invert_if(invert, pin.o1[bit]), | ||
o_dataout=p_negedge, | ||
o_dataout_b=n_negedge, | ||
) | ||
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whitequark
Contributor
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return m | ||
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This seems wrong; on most FPGA families, the IO buffer follows the DDR buffer, not precedes it.