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base repository: m-labs/nmigen
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Sep 12, 2019

  1. lib.cdc: adjust MultiReg for new CDC primitive conventions.

    Refs #97.
    whitequark committed Sep 12, 2019
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    8f659b6 View commit details
  2. Copy the full SHA
    9893e3c View commit details
  3. lib.io: style. NFC.

    whitequark committed Sep 12, 2019
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    73244f2 View commit details
Showing with 27 additions and 14 deletions.
  1. +13 −1 nmigen/compat/genlib/cdc.py
  2. +1 −1 nmigen/compat/genlib/resetsync.py
  3. +9 −9 nmigen/lib/cdc.py
  4. +2 −2 nmigen/lib/fifo.py
  5. +2 −1 nmigen/lib/io.py
14 changes: 13 additions & 1 deletion nmigen/compat/genlib/cdc.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
import warnings

from ...tools import deprecated
from ...lib.cdc import MultiReg
from ...lib.cdc import MultiReg as NativeMultiReg
from ...hdl.ast import *
from ..fhdl.module import CompatModule
from ..fhdl.structure import If
@@ -8,6 +10,16 @@
__all__ = ["MultiReg", "GrayCounter", "GrayDecoder"]


class MultiReg(NativeMultiReg):
def __init__(self, i, o, odomain="sync", n=2, reset=0):
if odomain != "sync":
warnings.warn("instead of `MultiReg(..., odomain={!r})`, "
"use `MultiReg(..., o_domain={!r})`"
.format(odomain, odomain),
DeprecationWarning, stacklevel=2)
super().__init__(i, o, o_domain=odomain, n=n, reset=reset)


@deprecated("instead of `migen.genlib.cdc.GrayCounter`, use `nmigen.lib.coding.GrayEncoder`")
class GrayCounter(CompatModule):
def __init__(self, width):
2 changes: 1 addition & 1 deletion nmigen/compat/genlib/resetsync.py
Original file line number Diff line number Diff line change
@@ -10,7 +10,7 @@
"a clock domain name as an argument, not a clock domain object")
class CompatResetSynchronizer(NativeResetSynchronizer):
def __init__(self, cd, async_reset):
super().__init__(async_reset, cd.name)
super().__init__(async_reset, domain=cd.name)


AsyncResetSynchronizer = CompatResetSynchronizer
18 changes: 9 additions & 9 deletions nmigen/lib/cdc.py
Original file line number Diff line number Diff line change
@@ -16,15 +16,15 @@ class MultiReg(Elaboratable):
Signal to be resynchronised
o : Signal(), out
Signal connected to synchroniser output
odomain : str
o_domain : str
Name of output clock domain
n : int
Number of flops between input and output.
reset : int
Reset value of the flip-flops. On FPGAs, even if ``reset_less`` is True, the MultiReg is
still set to this value during initialization.
reset_less : bool
If True (the default), this MultiReg is unaffected by ``odomain`` reset.
If True (the default), this MultiReg is unaffected by ``o_domain`` reset.
See "Note on Reset" below.
Platform override
@@ -42,17 +42,17 @@ class MultiReg(Elaboratable):
consider setting ``reset_less`` to False if any of the following is true:
- You are targeting an ASIC, or an FPGA that does not allow arbitrary initial flip-flop states;
- Your design features warm (non-power-on) resets of ``odomain``, so the one-time
- Your design features warm (non-power-on) resets of ``o_domain``, so the one-time
initialization at power on is insufficient;
- Your design features a sequenced reset, and the MultiReg must maintain its reset value until
``odomain`` reset specifically is deasserted.
``o_domain`` reset specifically is deasserted.
MultiReg is reset by the ``odomain`` reset only.
MultiReg is reset by the ``o_domain`` reset only.
"""
def __init__(self, i, o, odomain="sync", n=2, reset=0, reset_less=True):
def __init__(self, i, o, *, o_domain="sync", n=2, reset=0, reset_less=True):
self.i = i
self.o = o
self.odomain = odomain
self.o_domain = o_domain

self._regs = [Signal(self.i.shape(), name="cdc{}".format(i), reset=reset,
reset_less=reset_less)
@@ -64,13 +64,13 @@ def elaborate(self, platform):

m = Module()
for i, o in zip((self.i, *self._regs), self._regs):
m.d[self.odomain] += o.eq(i)
m.d[self.o_domain] += o.eq(i)
m.d.comb += self.o.eq(self._regs[-1])
return m


class ResetSynchronizer(Elaboratable):
def __init__(self, arst, domain="sync", n=2):
def __init__(self, arst, *, domain="sync", n=2):
self.arst = arst
self.domain = domain

4 changes: 2 additions & 2 deletions nmigen/lib/fifo.py
Original file line number Diff line number Diff line change
@@ -315,7 +315,7 @@ def elaborate(self, platform):
produce_enc = m.submodules.produce_enc = \
GrayEncoder(self._ctr_bits)
produce_cdc = m.submodules.produce_cdc = \
MultiReg(produce_w_gry, produce_r_gry, odomain="read")
MultiReg(produce_w_gry, produce_r_gry, o_domain="read")
m.d.comb += produce_enc.i.eq(produce_w_nxt),
m.d.write += produce_w_gry.eq(produce_enc.o)

@@ -324,7 +324,7 @@ def elaborate(self, platform):
consume_enc = m.submodules.consume_enc = \
GrayEncoder(self._ctr_bits)
consume_cdc = m.submodules.consume_cdc = \
MultiReg(consume_r_gry, consume_w_gry, odomain="write")
MultiReg(consume_r_gry, consume_w_gry, o_domain="write")
m.d.comb += consume_enc.i.eq(consume_r_nxt)
m.d.read += consume_r_gry.eq(consume_enc.o)

3 changes: 2 additions & 1 deletion nmigen/lib/io.py
Original file line number Diff line number Diff line change
@@ -102,4 +102,5 @@ def __init__(self, width, dir, xdr=0, name=None, src_loc_at=0):
self.dir = dir
self.xdr = xdr

super().__init__(pin_layout(self.width, self.dir, self.xdr), name=name, src_loc_at=src_loc_at + 1)
super().__init__(pin_layout(self.width, self.dir, self.xdr),
name=name, src_loc_at=src_loc_at + 1)