from nmigen import *
from nmigen.cli import main
from nmigen.asserts import *


class TestCase(Elaboratable):
    def __init__(self):
        self.input = Signal(8)
        self.output = Signal()

    def elaborate(self, platform):
        m = Module()

        with m.Switch(self.input):
            with m.Case(0b00000000):
                m.d.comb += self.output.eq(1)
            with m.Case("1???0000"):
                m.d.comb += self.output.eq(0)
            with m.Default():
                m.d.comb += self.output.eq(1)
        return m


if __name__ == "__main__":
    clk = Signal()
    rst = Signal()

    pos = ClockDomain()
    pos.clk = clk
    pos.rst = rst

    testcase = TestCase()

    m = Module()
    m.domains.pos = pos
    m.submodules.testcase = testcase

    main(
        m,
        ports=[clk, rst, testcase.input, testcase.output],
        platform="formal")