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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 29253295eea8
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Oct 13, 2019

  1. hdl.ir: allow ClockSignal and ResetSignal in ports.

    Fixes #248.
    whitequark committed Oct 13, 2019
    Copy the full SHA
    2925329 View commit details
Showing with 14 additions and 2 deletions.
  1. +1 −0 nmigen/hdl/ir.py
  2. +2 −2 nmigen/hdl/xfrm.py
  3. +11 −0 nmigen/test/test_hdl_ir.py
1 change: 1 addition & 0 deletions nmigen/hdl/ir.py
Original file line number Diff line number Diff line change
@@ -540,6 +540,7 @@ def prepare(self, ports=None, missing_domain=lambda name: ClockDomain(name)):
if ports is None:
fragment._propagate_ports(ports=(), all_undef_as_ports=True)
else:
ports = map(DomainLowerer(fragment.domains).on_value, ports)
new_ports = []
for cd in new_domains:
new_ports.append(cd.clk)
4 changes: 2 additions & 2 deletions nmigen/hdl/xfrm.py
Original file line number Diff line number Diff line change
@@ -486,8 +486,8 @@ def map_drivers(self, fragment, new_fragment):


class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer):
def __init__(self):
self.domains = None
def __init__(self, domains=None):
self.domains = domains

def _resolve(self, domain, context):
if domain not in self.domains:
11 changes: 11 additions & 0 deletions nmigen/test/test_hdl_ir.py
Original file line number Diff line number Diff line change
@@ -264,6 +264,17 @@ def test_inout(self):
(s, "io")
]))

def test_clk_rst(self):
sync = ClockDomain()
f = Fragment()
f.add_domains(sync)

f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync")))
self.assertEqual(f.ports, SignalDict([
(sync.clk, "i"),
(sync.rst, "i"),
]))


class FragmentDomainsTestCase(FHDLTestCase):
def test_iter_signals(self):