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ClockSignal() != sync.clk? #248

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RobertBaruch opened this issue Oct 12, 2019 · 1 comment
Closed

ClockSignal() != sync.clk? #248

RobertBaruch opened this issue Oct 12, 2019 · 1 comment
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backend:RTLIL bug
Milestone
0.1

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@RobertBaruch
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The following results in an error:

from nmigen.cli import main
from nmigen import *


class ThingBlock(Elaboratable):
    def __init__(self):
        pass

    def elaborate(self, platform: str):
        m = Module()

        return m


if __name__ == "__main__":
    sync = ClockDomain(name="sync")
    clk = ClockSignal()  # fails
    rst = ResetSignal()
    # clk = sync.clk # succeeds
    # rst = sync.rst

    block = ThingBlock()

    m = Module()
    m.submodules += block

    main(m, ports=[clk, rst])

The error:

$ pip3 show nmigen
Name: nmigen
Version: 0.1.dev719+gb90687c

$ python3 t.py generate -t v
Traceback (most recent call last):
  File "t.py", line 27, in <module>
    main(m, ports=[clk, rst])
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/cli.py", line 76, in main
    main_runner(parser, parser.parse_args(), *args, **kwargs)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/cli.py", line 58, in main_runner
    output = verilog.convert(fragment, name=name, ports=ports)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/verilog.py", line 75, in convert
    rtlil_text = rtlil.convert(*args, **kwargs)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 989, in convert
    il_text, name_map = convert_fragment(fragment, name)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 983, in convert_fragment
    _convert_fragment(builder, fragment, name_map, hierarchy=(name,))
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 784, in _convert_fragment
    compiler_state.resolve_curr(signal)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 307, in resolve_curr
    wire_curr, wire_next = self.resolve(signal, prefix)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 291, in resolve
    wire_name = signal.name
AttributeError: 'ClockSignal' object has no attribute 'name'
Error in sys.excepthook:
Traceback (most recent call last):
  File "/usr/lib/python3/dist-packages/apport_python_hook.py", line 63, in apport_excepthook
    from apport.fileutils import likely_packaged, get_recent_crashes
  File "/usr/lib/python3/dist-packages/apport/__init__.py", line 5, in <module>
    from apport.report import Report
  File "/usr/lib/python3/dist-packages/apport/report.py", line 30, in <module>
    import apport.fileutils
  File "/usr/lib/python3/dist-packages/apport/fileutils.py", line 23, in <module>
    from apport.packaging_impl import impl as packaging
  File "/usr/lib/python3/dist-packages/apport/packaging_impl.py", line 23, in <module>
    import apt
  File "/usr/lib/python3/dist-packages/apt/__init__.py", line 23, in <module>
    import apt_pkg
ModuleNotFoundError: No module named 'apt_pkg'

Original exception was:
Traceback (most recent call last):
  File "t.py", line 27, in <module>
    main(m, ports=[clk, rst])
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/cli.py", line 76, in main
    main_runner(parser, parser.parse_args(), *args, **kwargs)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/cli.py", line 58, in main_runner
    output = verilog.convert(fragment, name=name, ports=ports)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/verilog.py", line 75, in convert
    rtlil_text = rtlil.convert(*args, **kwargs)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 989, in convert
    il_text, name_map = convert_fragment(fragment, name)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 983, in convert_fragment
    _convert_fragment(builder, fragment, name_map, hierarchy=(name,))
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 784, in _convert_fragment
    compiler_state.resolve_curr(signal)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 307, in resolve_curr
    wire_curr, wire_next = self.resolve(signal, prefix)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/rtlil.py", line 291, in resolve
    wire_name = signal.name
AttributeError: 'ClockSignal' object has no attribute 'name'

This seems to be in contradiction to the comments in the code in ast.py:

@final
class ClockSignal(Value):
    """Clock signal for a clock domain.

    Any ``ClockSignal`` is equivalent to ``cd.clk`` for a clock domain with the corresponding name.
    All of these signals ultimately refer to the same signal, but they can be manipulated
    independently of the clock domain, even before the clock domain is created.

    Parameters
    ----------
    domain : str
        Clock domain to obtain a clock signal for. Defaults to ``"sync"``.
    """
@whitequark
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Contributor

ClockSignal and ResetSignal are lazily bound (that's their point) and there's currently no code that would handle them for ports.

@whitequark whitequark added this to the 0.1 milestone Oct 12, 2019
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@whitequark @RobertBaruch