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base repository: m-labs/nmigen
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compare: 706bfaf5e185
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  • 2 commits
  • 13 files changed
  • 1 contributor

Commits on Oct 11, 2019

  1. hdl.ast: add an explicit Shape class, included in prelude.

    Shapes have long been a part of nMigen, but represented using tuples.
    This commit adds a Shape class (using namedtuple for backwards
    compatibility), and accepts anything castable to Shape (including
    enums, ranges, etc) anywhere a tuple was accepted previously.
    
    In addition, `signed(n)` and `unsigned(n)` are added as aliases for
    `Shape(n, signed=True)` and `Shape(n, signed=False)`, transforming
    code such as `Signal((8, True))` to `Signal(signed(8))`.
    These aliases are also included in prelude.
    
    Preparation for #225.
    whitequark committed Oct 11, 2019
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    6aabdc0 View commit details
  2. hdl.ast: deprecate Signal.{range,enum}.

    Although constructor methods can improve clarity, there are many
    contexts in which it is useful to use range() as a shape: notably
    Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
    these constructor methods everywhere (which is not even easily
    possible for Layout), use casting to Shape, introduced in 6aabdc0.
    
    Fixes #225.
    whitequark committed Oct 11, 2019
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    706bfaf View commit details
2 changes: 1 addition & 1 deletion examples/basic/fsm.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,7 @@ def __init__(self, divisor):
def elaborate(self, platform):
m = Module()

ctr = Signal.range(self.divisor)
ctr = Signal(range(self.divisor))
stb = Signal()
with m.If(ctr == 0):
m.d.sync += ctr.eq(self.divisor - 1)
2 changes: 1 addition & 1 deletion examples/basic/por.py
Original file line number Diff line number Diff line change
@@ -7,7 +7,7 @@
cd_sync = ClockDomain()
m.domains += cd_por, cd_sync

delay = Signal.range(256, reset=255)
delay = Signal(range(256), reset=255)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
m.d.comb += [
8 changes: 4 additions & 4 deletions examples/basic/uart.py
Original file line number Diff line number Diff line change
@@ -31,9 +31,9 @@ def __init__(self, divisor, data_bits=8):
def elaborate(self, platform):
m = Module()

tx_phase = Signal.range(self.divisor)
tx_phase = Signal(range(self.divisor))
tx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
tx_count = Signal.range(len(tx_shreg) + 1)
tx_count = Signal(range(len(tx_shreg) + 1))

m.d.comb += self.tx_o.eq(tx_shreg[0])
with m.If(tx_count == 0):
@@ -54,9 +54,9 @@ def elaborate(self, platform):
tx_phase.eq(self.divisor - 1),
]

rx_phase = Signal.range(self.divisor)
rx_phase = Signal(range(self.divisor))
rx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
rx_count = Signal.range(len(rx_shreg) + 1)
rx_count = Signal(range(len(rx_shreg) + 1))

m.d.comb += self.rx_data.eq(rx_shreg[1:-1])
with m.If(rx_count == 0):
1 change: 1 addition & 0 deletions nmigen/hdl/__init__.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
from .ast import Shape, unsigned, signed
from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
from .dsl import Module
from .cd import ClockDomain
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