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base repository: m-labs/nmigen-boards
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compare: bd9877f0ec17
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Oct 11, 2019

  1. resources: add conn= argument to every factory.

    whitequark committed Oct 11, 2019
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    25e247c View commit details
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    44fdd4f View commit details
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    bd9877f View commit details
Showing with 120 additions and 125 deletions.
  1. +15 −28 nmigen_boards/icebreaker.py
  2. +1 −1 nmigen_boards/mercury.py
  3. +10 −9 nmigen_boards/resources/display.py
  4. +29 −27 nmigen_boards/resources/interface.py
  5. +59 −54 nmigen_boards/resources/memory.py
  6. +6 −6 nmigen_boards/resources/user.py
43 changes: 15 additions & 28 deletions nmigen_boards/icebreaker.py
Original file line number Diff line number Diff line change
@@ -44,35 +44,22 @@ class ICEBreakerPlatform(LatticeICE40Platform):
# p.add_resources(p.break_off_pmod)
# pmod_btn = plat.request("user_btn")
break_off_pmod = [
Resource("user_btn", 1, Pins("9", dir="i", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_btn", 2, Pins("4", dir="i", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_btn", 3, Pins("10", dir="i", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),

Resource("user_led", 2, Pins("7", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_led", 3, Pins("1", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_led", 4, Pins("2", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_led", 5, Pins("8", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_led", 6, Pins("3", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
*LEDResources(pins={2: "7", 3: "1", 4: "2", 5: "8", 6: "3"}, conn=("pmod", 2),
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# Semantic aliases
Resource("led_r", 1, Pins("7", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led_g", 1, Pins("1", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led_g", 2, Pins("2", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led_g", 3, Pins("8", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led_g", 4, Pins("3", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),

# Color-specific aliases
Resource("user_ledr", 1, Pins("7", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_ledg", 1, Pins("1", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_ledg", 2, Pins("2", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_ledg", 3, Pins("8", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_ledg", 4, Pins("3", dir="o", conn=("pmod", 2)),
Attrs(IO_STANDARD="SB_LVCMOS"))
*ButtonResources(pins={1: "9", 2: "4", 3: "10"}, conn=("pmod", 2),
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
]

def toolchain_program(self, products, name):
2 changes: 1 addition & 1 deletion nmigen_boards/mercury.py
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ class MercuryPlatform(XilinxSpartan3APlatform):
Resource("clk50", 0, Pins("P43", dir="i"),
Attrs(IOSTANDARD="LVCMOS33"), Clock(50e6)),

Resource("user_btn", 0, Pins("P41", dir="i"),
Resource("button", 0, Pins("P41", dir="i"),
Attrs(IOSTANDARD="LVTTL")),

# The serial interface and flash memory have a shared SPI bus.
19 changes: 10 additions & 9 deletions nmigen_boards/resources/display.py
Original file line number Diff line number Diff line change
@@ -4,17 +4,18 @@
__all__ = ["Display7SegResource"]


def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False, attrs=None):
def Display7SegResource(*args, a, b, c, d, e, f, g, dp=None, invert=False,
conn=None, attrs=None):
ios = []
ios.append(Subsignal("a", Pins(a, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("c", Pins(c, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("d", Pins(d, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("e", Pins(e, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("f", Pins(f, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("a", Pins(a, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("c", Pins(c, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("d", Pins(d, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("e", Pins(e, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("f", Pins(f, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, conn=conn, assert_width=1)))
if dp is not None:
ios.append(Subsignal("dp", Pins(dp, dir="o", assert_width=1)))
ios.append(Subsignal("dp", Pins(dp, dir="o", conn=conn, assert_width=1)))
if attrs is not None:
ios.append(attrs)
return Resource.family(*args, default_name="display_7seg", ios=ios)
56 changes: 29 additions & 27 deletions nmigen_boards/resources/interface.py
Original file line number Diff line number Diff line change
@@ -5,68 +5,70 @@


def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
attrs=None):
conn=None, attrs=None):
io = []
io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1)))
if rts is not None:
io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
io.append(Subsignal("rts", Pins(rts, dir="o", conn=conn, assert_width=1)))
if cts is not None:
io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
io.append(Subsignal("cts", Pins(cts, dir="i", conn=conn, assert_width=1)))
if dtr is not None:
io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
io.append(Subsignal("dtr", Pins(dtr, dir="o", conn=conn, assert_width=1)))
if dsr is not None:
io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
io.append(Subsignal("dsr", Pins(dsr, dir="i", conn=conn, assert_width=1)))
if dcd is not None:
io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
io.append(Subsignal("dcd", Pins(dcd, dir="i", conn=conn, assert_width=1)))
if ri is not None:
io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
io.append(Subsignal("ri", Pins(ri, dir="i", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="uart", ios=io)


def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
def IrDAResource(number, *, rx, tx, en=None, sd=None,
conn=None, attrs=None):
# Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
# be specified, and it is mapped to a logic level en subsignal.
assert (en is not None) ^ (sd is not None)

io = []
io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1)))
if en is not None:
io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
io.append(Subsignal("en", Pins(en, dir="o", conn=conn, assert_width=1)))
if sd is not None:
io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
io.append(Subsignal("en", PinsN(sd, dir="o", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource("irda", number, *io)


def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, attrs=None, role="host"):
def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None,
conn=None, attrs=None, role="host"):
assert role in ("host", "device")

io = []
if role == "host":
io.append(Subsignal("cs", PinsN(cs, dir="o")))
io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="i", conn=conn, assert_width=1)))
else: # device
io.append(Subsignal("cs", PinsN(cs, dir="i", assert_width=1)))
io.append(Subsignal("clk", Pins(clk, dir="i", assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="i", assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="oe", assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("clk", Pins(clk, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="oe", conn=conn, assert_width=1)))
if int is not None:
if role == "host":
io.append(Subsignal("int", Pins(int, dir="i")))
io.append(Subsignal("int", Pins(int, dir="i", conn=conn)))
else:
io.append(Subsignal("int", Pins(int, dir="oe", assert_width=1)))
io.append(Subsignal("int", Pins(int, dir="oe", conn=conn, assert_width=1)))
if reset is not None:
if role == "host":
io.append(Subsignal("reset", Pins(reset, dir="o")))
io.append(Subsignal("reset", Pins(reset, dir="o", conn=conn)))
else:
io.append(Subsignal("reset", Pins(reset, dir="i", assert_width=1)))
io.append(Subsignal("reset", Pins(reset, dir="i", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="spi", ios=io)
113 changes: 59 additions & 54 deletions nmigen_boards/resources/memory.py
Original file line number Diff line number Diff line change
@@ -7,152 +7,157 @@
]


def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None,
conn=None, attrs=None):
resources = []

io_all = []
if attrs is not None:
io_all.append(attrs)
io_all.append(Subsignal("cs", PinsN(cs, dir="o")))
io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io_all.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))

io_1x = list(io_all)
io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1)))
io_1x.append(Subsignal("miso", Pins(miso, dir="i", conn=conn, assert_width=1)))
if wp is not None and hold is not None:
io_1x.append(Subsignal("wp", PinsN(wp, dir="o", assert_width=1)))
io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
io_1x.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1)))
io_1x.append(Subsignal("hold", PinsN(hold, dir="o", conn=conn, assert_width=1)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
name_suffix="1x"))

io_2x = list(io_all)
io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io", conn=conn,
assert_width=2)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
name_suffix="2x"))

if wp is not None and hold is not None:
io_4x = list(io_all)
io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io", conn=conn,
assert_width=4)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
name_suffix="4x"))

return resources


def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None,
cd=None, wp=None, attrs=None):
def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None, cd=None, wp=None,
conn=None, attrs=None):
resources = []

io_common = []
if attrs is not None:
io_common.append(attrs)
if cd is not None:
io_common.append(Subsignal("cd", Pins(cd, dir="i", assert_width=1)))
io_common.append(Subsignal("cd", Pins(cd, dir="i", conn=conn, assert_width=1)))
if wp is not None:
io_common.append(Subsignal("wp", PinsN(wp, dir="i", assert_width=1)))
io_common.append(Subsignal("wp", PinsN(wp, dir="i", conn=conn, assert_width=1)))

io_native = list(io_common)
io_native.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io_native.append(Subsignal("cmd", Pins(cmd, dir="o", assert_width=1)))
io_native.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
io_native.append(Subsignal("cmd", Pins(cmd, dir="o", conn=conn, assert_width=1)))

io_1bit = list(io_native)
io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", assert_width=1)))
io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", conn=conn, assert_width=1)))
if dat3 is not None:
# DAT3 has a pullup and works as electronic card detect
io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", assert_width=1)))
io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", conn=conn, assert_width=1)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
name_suffix="1bit"))

if dat1 is not None and dat2 is not None and dat3 is not None:
io_4bit = list(io_native)
io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
assert_width=4)))
conn=conn, assert_width=4)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
name_suffix="4bit"))

if dat3 is not None:
io_spi = list(io_common)
# DAT3/CS# has a pullup and doubles as electronic card detect
io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", assert_width=1)))
io_spi.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", assert_width=1)))
io_spi.append(Subsignal("miso", Pins(dat0, dir="i", assert_width=1)))
io_spi.append(Subsignal("cs", PinsN(dat3, dir="io", conn=conn, assert_width=1)))
io_spi.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", conn=conn, assert_width=1)))
io_spi.append(Subsignal("miso", Pins(dat0, dir="i", conn=conn, assert_width=1)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
name_suffix="spi"))

return resources


def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
def SRAMResource(*args, cs, oe=None, we, a, d, dm=None,
conn=None, attrs=None):
io = []
io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
if oe is not None:
# Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("d", Pins(d, dir="io")))
io.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
io.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
io.append(Subsignal("d", Pins(d, dir="io", conn=conn)))
if dm is not None:
io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#"
io.append(Subsignal("dm", Pins(dm, dir="o", conn=conn))) # dm="LB# UB#"
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sram", ios=io)


def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm, attrs=None):
def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm=None,
conn=None, attrs=None):
io = []
io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, conn=None, assert_width=1)))
if cke is not None:
io.append(Subsignal("clk_en", Pins(cke, dir="o", assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io.append(Subsignal("ras", PinsN(ras, dir="o", assert_width=1)))
io.append(Subsignal("cas", PinsN(cas, dir="o", assert_width=1)))
io.append(Subsignal("ba", Pins(ba, dir="o")))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("dq", Pins(dq, dir="io")))
io.append(Subsignal("clk_en", Pins(cke, dir="o", conn=conn, conn=None, assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, conn=None, assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", conn=conn, conn=None, assert_width=1)))
io.append(Subsignal("ras", PinsN(ras, dir="o", conn=conn, conn=None, assert_width=1)))
io.append(Subsignal("cas", PinsN(cas, dir="o", conn=conn, conn=None, assert_width=1)))
io.append(Subsignal("ba", Pins(ba, dir="o", conn=conn, conn=None)))
io.append(Subsignal("a", Pins(a, dir="o", conn=conn, conn=None)))
io.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, conn=None)))
if dqm is not None:
io.append(Subsignal("dqm", Pins(dqm, dir="o")))
io.append(Subsignal("dqm", Pins(dqm, dir="o", conn=conn, conn=None))) # dqm="LDQM# UDQM#"
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sdram", ios=io)


def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq, attrs=None):
def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq,
conn=None, attrs=None):
resources = []

io_common = []
if rst is not None:
io_common.append(Subsignal("rst", Pins(rst, dir="o", assert_width=1)))
io_common.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
io_common.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
io_common.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io_common.append(Subsignal("wp", PinsN(wp, dir="o", assert_width=1)))
io_common.append(Subsignal("rdy", Pins(by, dir="i", assert_width=1)))
io_common.append(Subsignal("rst", Pins(rst, dir="o", conn=conn, assert_width=1)))
io_common.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn, assert_width=1)))
io_common.append(Subsignal("oe", PinsN(oe, dir="o", conn=conn, assert_width=1)))
io_common.append(Subsignal("we", PinsN(we, dir="o", conn=conn, assert_width=1)))
io_common.append(Subsignal("wp", PinsN(wp, dir="o", conn=conn, assert_width=1)))
io_common.append(Subsignal("rdy", Pins(by, dir="i", conn=conn, assert_width=1)))

if byte is None:
io_8bit = list(io_common)
io_8bit.append(Subsignal("a", Pins(a, dir="o")))
io_8bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=8)))
io_8bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
io_8bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=8)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
name_suffix="8bit"))
else:
*dq_0_14, dq15_am1 = dq.split()

# If present in a requested resource, this pin needs to be strapped correctly.
io_common.append(Subsignal("byte", PinsN(byte, dir="o", assert_width=1)))
io_common.append(Subsignal("byte", PinsN(byte, dir="o", conn=conn, assert_width=1)))

io_8bit = list(io_common)
io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o")))
io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", assert_width=8)))
io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o", conn=conn)))
io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", conn=conn,
assert_width=8)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
name_suffix="8bit"))

io_16bit = list(io_common)
io_16bit.append(Subsignal("a", Pins(a, dir="o")))
io_16bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=16)))
io_16bit.append(Subsignal("a", Pins(a, dir="o", conn=conn)))
io_16bit.append(Subsignal("dq", Pins(dq, dir="io", conn=conn, assert_width=16)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
name_suffix="16bit"))

12 changes: 6 additions & 6 deletions nmigen_boards/resources/user.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
__all__ = ["LEDResources", "RGBLEDResource", "ButtonResources", "SwitchResources"]


def _SplitResources(*args, pins, invert=False, attrs=None, default_name, dir):
def _SplitResources(*args, pins, invert=False, conn=None, attrs=None, default_name, dir):
assert isinstance(pins, (str, list, dict))

if isinstance(pins, str):
@@ -14,7 +14,7 @@ def _SplitResources(*args, pins, invert=False, attrs=None, default_name, dir):

resources = []
for number, pin in pins.items():
ios = [Pins(pin, dir=dir, invert=invert)]
ios = [Pins(pin, dir=dir, invert=invert, conn=conn)]
if attrs is not None:
ios.append(attrs)
resources.append(Resource.family(*args, number, default_name=default_name, ios=ios))
@@ -25,11 +25,11 @@ def LEDResources(*args, **kwargs):
return _SplitResources(*args, **kwargs, default_name="led", dir="o")


def RGBLEDResource(*args, r, g, b, invert=False, attrs=None):
def RGBLEDResource(*args, r, g, b, invert=False, conn=None, attrs=None):
ios = []
ios.append(Subsignal("r", Pins(r, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, assert_width=1)))
ios.append(Subsignal("r", Pins(r, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("g", Pins(g, dir="o", invert=invert, conn=conn, assert_width=1)))
ios.append(Subsignal("b", Pins(b, dir="o", invert=invert, conn=conn, assert_width=1)))
if attrs is not None:
ios.append(attrs)
return Resource.family(*args, default_name="rgb_led", ios=ios)