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base repository: m-labs/nmigen
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compare: db960e7c30f7
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  • 1 commit
  • 16 files changed
  • 1 contributor

Commits on Oct 11, 2019

  1. Consistently use {!r}, not '{!r}' in diagnostics.

    This can cause confusion:
      * If the erroneous object is None, it is printed as 'None', which
        appears as a string (and could be the result of converting None
        to a string.)
      * If the erroneous object is a string, it is printed as ''<val>'',
        which is a rather strange combination of quotes.
    whitequark committed Oct 11, 2019
    Copy the full SHA
    db960e7 View commit details
8 changes: 4 additions & 4 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -420,7 +420,7 @@ def _check_process(process):
if inspect.isgeneratorfunction(process):
process = process()
if not (inspect.isgenerator(process) or inspect.iscoroutine(process)):
raise TypeError("Cannot add a process '{!r}' because it is not a generator or "
raise TypeError("Cannot add a process {!r} because it is not a generator or "
"a generator function"
.format(process))
return process
@@ -744,12 +744,12 @@ def _run_process(self, process):
lhs_signals = cmd.lhs._lhs_signals()
for signal in lhs_signals:
if not signal in self._signals:
raise ValueError("Process '{}' sent a request to set signal '{!r}', "
raise ValueError("Process '{}' sent a request to set signal {!r}, "
"which is not a part of simulation"
.format(self._name_process(process), signal))
signal_slot = self._signal_slots[signal]
if self._comb_signals[signal_slot]:
raise ValueError("Process '{}' sent a request to set signal '{!r}', "
raise ValueError("Process '{}' sent a request to set signal {!r}, "
"which is a part of combinatorial assignment in "
"simulation"
.format(self._name_process(process), signal))
@@ -780,7 +780,7 @@ def _run_process(self, process):
continue

else:
raise TypeError("Received unsupported command '{!r}' from process '{}'"
raise TypeError("Received unsupported command {!r} from process '{}'"
.format(cmd, self._name_process(process)))

cmd = process.send(None)
36 changes: 18 additions & 18 deletions nmigen/hdl/ast.py
Original file line number Diff line number Diff line change
@@ -396,7 +396,7 @@ def __init__(self, value, shape=None):
shape = shape, self.value < 0
self.width, self.signed = shape
if not isinstance(self.width, int) or self.width < 0:
raise TypeError("Width must be a non-negative integer, not '{!r}'"
raise TypeError("Width must be a non-negative integer, not {!r}"
.format(self.width))
self.value = self.normalize(self.value, shape)

@@ -429,7 +429,7 @@ def __init__(self, shape, *, src_loc_at=0):
shape = shape, False
self.width, self.signed = shape
if not isinstance(self.width, int) or self.width < 0:
raise TypeError("Width must be a non-negative integer, not '{!r}'"
raise TypeError("Width must be a non-negative integer, not {!r}"
.format(self.width))

def shape(self):
@@ -559,9 +559,9 @@ def Mux(sel, val1, val0):
class Slice(Value):
def __init__(self, value, start, end, *, src_loc_at=0):
if not isinstance(start, int):
raise TypeError("Slice start must be an integer, not '{!r}'".format(start))
raise TypeError("Slice start must be an integer, not {!r}".format(start))
if not isinstance(end, int):
raise TypeError("Slice end must be an integer, not '{!r}'".format(end))
raise TypeError("Slice end must be an integer, not {!r}".format(end))

n = len(value)
if start not in range(-(n+1), n+1):
@@ -597,9 +597,9 @@ def __repr__(self):
class Part(Value):
def __init__(self, value, offset, width, stride=1, *, src_loc_at=0):
if not isinstance(width, int) or width < 0:
raise TypeError("Part width must be a non-negative integer, not '{!r}'".format(width))
raise TypeError("Part width must be a non-negative integer, not {!r}".format(width))
if not isinstance(stride, int) or stride <= 0:
raise TypeError("Part stride must be a positive integer, not '{!r}'".format(stride))
raise TypeError("Part stride must be a positive integer, not {!r}".format(stride))

super().__init__(src_loc_at=src_loc_at)
self.value = value
@@ -693,7 +693,7 @@ class Repl(Value):
"""
def __init__(self, value, count, *, src_loc_at=0):
if not isinstance(count, int) or count < 0:
raise TypeError("Replication count must be a non-negative integer, not '{!r}'"
raise TypeError("Replication count must be a non-negative integer, not {!r}"
.format(count))

super().__init__(src_loc_at=src_loc_at)
@@ -770,7 +770,7 @@ def __init__(self, shape=None, *, name=None, reset=0, reset_less=False, min=None
DeprecationWarning, stacklevel=2 + src_loc_at)

if name is not None and not isinstance(name, str):
raise TypeError("Name must be a string, not '{!r}'".format(name))
raise TypeError("Name must be a string, not {!r}".format(name))
self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal")

if shape is None:
@@ -798,7 +798,7 @@ def __init__(self, shape=None, *, name=None, reset=0, reset_less=False, min=None
self.width, self.signed = shape

if not isinstance(self.width, int) or self.width < 0:
raise TypeError("Width must be a non-negative integer, not '{!r}'".format(self.width))
raise TypeError("Width must be a non-negative integer, not {!r}".format(self.width))

reset_width = bits_for(reset, self.signed)
if reset != 0 and reset_width > self.width:
@@ -913,7 +913,7 @@ class ClockSignal(Value):
def __init__(self, domain="sync", *, src_loc_at=0):
super().__init__(src_loc_at=src_loc_at)
if not isinstance(domain, str):
raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain))
raise TypeError("Clock domain name must be a string, not {!r}".format(domain))
if domain == "comb":
raise ValueError("Domain '{}' does not have a clock".format(domain))
self.domain = domain
@@ -949,7 +949,7 @@ class ResetSignal(Value):
def __init__(self, domain="sync", allow_reset_less=False, *, src_loc_at=0):
super().__init__(src_loc_at=src_loc_at)
if not isinstance(domain, str):
raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain))
raise TypeError("Clock domain name must be a string, not {!r}".format(domain))
if domain == "comb":
raise ValueError("Domain '{}' does not have a reset".format(domain))
self.domain = domain
@@ -1221,7 +1221,7 @@ def wrap(obj):
if isinstance(obj, Statement):
return _StatementList([obj])
else:
raise TypeError("Object '{!r}' is not an nMigen statement".format(obj))
raise TypeError("Object {!r} is not an nMigen statement".format(obj))


@final
@@ -1311,7 +1311,7 @@ def __init__(self, test, cases, *, src_loc=None, src_loc_at=0, case_src_locs={})
elif isinstance(key, Enum):
key = format(key.value, "b").rjust(len(self.test), "0")
else:
raise TypeError("Object '{!r}' cannot be used as a switch key"
raise TypeError("Object {!r} cannot be used as a switch key"
.format(key))
assert len(key) == len(self.test)
new_keys = (*new_keys, key)
@@ -1500,7 +1500,7 @@ def __init__(self, value):
elif isinstance(self.value, Initial):
self._hash = 0
else: # :nocov:
raise TypeError("Object '{!r}' cannot be used as a key in value collections"
raise TypeError("Object {!r} cannot be used as a key in value collections"
.format(self.value))

def __hash__(self):
@@ -1548,7 +1548,7 @@ def __eq__(self, other):
elif isinstance(self.value, Initial):
return True
else: # :nocov:
raise TypeError("Object '{!r}' cannot be used as a key in value collections"
raise TypeError("Object {!r} cannot be used as a key in value collections"
.format(self.value))

def __lt__(self, other):
@@ -1566,7 +1566,7 @@ def __lt__(self, other):
self.value.start < other.value.start and
self.value.end < other.value.end)
else: # :nocov:
raise TypeError("Object '{!r}' cannot be used as a key in value collections")
raise TypeError("Object {!r} cannot be used as a key in value collections")

def __repr__(self):
return "<{}.ValueKey {!r}>".format(__name__, self.value)
@@ -1592,7 +1592,7 @@ def __init__(self, signal):
elif type(signal) is ResetSignal:
self._intern = (2, signal.domain)
else:
raise TypeError("Object '{!r}' is not an nMigen signal".format(signal))
raise TypeError("Object {!r} is not an nMigen signal".format(signal))

def __hash__(self):
return hash(self._intern)
@@ -1604,7 +1604,7 @@ def __eq__(self, other):

def __lt__(self, other):
if type(other) is not SignalKey:
raise TypeError("Object '{!r}' cannot be compared to a SignalKey".format(signal))
raise TypeError("Object {!r} cannot be compared to a SignalKey".format(signal))
return self._intern < other._intern

def __repr__(self):
2 changes: 1 addition & 1 deletion nmigen/hdl/dsl.py
Original file line number Diff line number Diff line change
@@ -454,7 +454,7 @@ def domain_name(domain):

def _add_submodule(self, submodule, name=None):
if not hasattr(submodule, "elaborate"):
raise TypeError("Trying to add '{!r}', which does not implement .elaborate(), as "
raise TypeError("Trying to add {!r}, which does not implement .elaborate(), as "
"a submodule".format(submodule))
if name == None:
self._anon_submodules.append(submodule)
2 changes: 1 addition & 1 deletion nmigen/hdl/ir.py
Original file line number Diff line number Diff line change
@@ -70,7 +70,7 @@ def get(obj, platform):
code = obj.elaborate.__code__
obj = obj.elaborate(platform)
else:
raise AttributeError("Object '{!r}' cannot be elaborated".format(obj))
raise AttributeError("Object {!r} cannot be elaborated".format(obj))
if obj is None and code is not None:
warnings.warn_explicit(
message=".elaborate() returned None; missing return statement?",
6 changes: 3 additions & 3 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -11,10 +11,10 @@
class Memory:
def __init__(self, *, width, depth, init=None, name=None, simulate=True):
if not isinstance(width, int) or width < 0:
raise TypeError("Memory width must be a non-negative integer, not '{!r}'"
raise TypeError("Memory width must be a non-negative integer, not {!r}"
.format(width))
if not isinstance(depth, int) or depth < 0:
raise TypeError("Memory depth must be a non-negative integer, not '{!r}'"
raise TypeError("Memory depth must be a non-negative integer, not {!r}"
.format(depth))

self.name = name or tracer.get_var_name(depth=2, default="$memory")
@@ -136,7 +136,7 @@ def __init__(self, memory, *, domain="sync", granularity=None):
if granularity is None:
granularity = memory.width
if not isinstance(granularity, int) or granularity < 0:
raise TypeError("Write port granularity must be a non-negative integer, not '{!r}'"
raise TypeError("Write port granularity must be a non-negative integer, not {!r}"
.format(granularity))
if granularity > memory.width:
raise ValueError("Write port granularity must not be greater than memory width "
6 changes: 3 additions & 3 deletions nmigen/hdl/xfrm.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,7 @@ def on_Initial(self, value):
pass # :nocov:

def on_unknown_value(self, value):
raise TypeError("Cannot transform value '{!r}'".format(value)) # :nocov:
raise TypeError("Cannot transform value {!r}".format(value)) # :nocov:

def replace_value_src_loc(self, value, new_value):
return True
@@ -209,7 +209,7 @@ def on_statements(self, stmts):
pass # :nocov:

def on_unknown_statement(self, stmt):
raise TypeError("Cannot transform statement '{!r}'".format(stmt)) # :nocov:
raise TypeError("Cannot transform statement {!r}".format(stmt)) # :nocov:

def replace_statement_src_loc(self, stmt, new_stmt):
return True
@@ -321,7 +321,7 @@ def __call__(self, value):
value._transforms_.append(self)
return value
else:
raise AttributeError("Object '{!r}' cannot be elaborated".format(value))
raise AttributeError("Object {!r} cannot be elaborated".format(value))


class TransformedElaboratable(Elaboratable):
2 changes: 1 addition & 1 deletion nmigen/lib/cdc.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@

def _check_stages(stages):
if not isinstance(stages, int) or stages < 1:
raise TypeError("Synchronization stage count must be a positive integer, not '{!r}'"
raise TypeError("Synchronization stage count must be a positive integer, not {!r}"
.format(stages))
if stages < 2:
raise ValueError("Synchronization stage count may not safely be less than 2")
4 changes: 2 additions & 2 deletions nmigen/lib/fifo.py
Original file line number Diff line number Diff line change
@@ -62,10 +62,10 @@ class FIFOInterface:

def __init__(self, *, width, depth, fwft):
if not isinstance(width, int) or width < 0:
raise TypeError("FIFO width must be a non-negative integer, not '{!r}'"
raise TypeError("FIFO width must be a non-negative integer, not {!r}"
.format(width))
if not isinstance(depth, int) or depth < 0:
raise TypeError("FIFO depth must be a non-negative integer, not '{!r}'"
raise TypeError("FIFO depth must be a non-negative integer, not {!r}"
.format(depth))
self.width = width
self.depth = depth
6 changes: 3 additions & 3 deletions nmigen/lib/io.py
Original file line number Diff line number Diff line change
@@ -13,13 +13,13 @@ def pin_layout(width, dir, xdr=0):
See :class:`Pin` for details.
"""
if not isinstance(width, int) or width < 1:
raise TypeError("Width must be a positive integer, not '{!r}'"
raise TypeError("Width must be a positive integer, not {!r}"
.format(width))
if dir not in ("i", "o", "oe", "io"):
raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not '{!r}'"""
raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not {!r}"""
.format(dir))
if not isinstance(xdr, int) or xdr < 0:
raise TypeError("Gearing ratio must be a non-negative integer, not '{!r}'"
raise TypeError("Gearing ratio must be a non-negative integer, not {!r}"
.format(xdr))

fields = []
20 changes: 10 additions & 10 deletions nmigen/test/test_hdl_ast.py
Original file line number Diff line number Diff line change
@@ -105,9 +105,9 @@ def test_shape(self):
self.assertEqual(Const(1, (4, True)).shape(), (4, True))
self.assertEqual(Const(0, (0, False)).shape(), (0, False))

def test_shape_bad(self):
def test_shape_wrong(self):
with self.assertRaises(TypeError,
msg="Width must be a non-negative integer, not '-1'"):
msg="Width must be a non-negative integer, not -1"):
Const(1, -1)

def test_normalization(self):
@@ -392,10 +392,10 @@ def test_start_end_negative(self):

def test_start_end_wrong(self):
with self.assertRaises(TypeError,
msg="Slice start must be an integer, not ''x''"):
msg="Slice start must be an integer, not 'x'"):
Slice(0, "x", 1)
with self.assertRaises(TypeError,
msg="Slice end must be an integer, not ''x''"):
msg="Slice end must be an integer, not 'x'"):
Slice(0, 1, "x")

def test_start_end_out_of_range(self):
@@ -430,7 +430,7 @@ def test_stride(self):
s1 = self.c.bit_select(self.s, 2)
self.assertEqual(s1.stride, 1)

def test_width_bad(self):
def test_width_wrong(self):
with self.assertRaises(TypeError):
self.c.bit_select(self.s, -1)

@@ -452,7 +452,7 @@ def test_stride(self):
s1 = self.c.word_select(self.s, 2)
self.assertEqual(s1.stride, 2)

def test_width_bad(self):
def test_width_wrong(self):
with self.assertRaises(TypeError):
self.c.word_select(self.s, 0)
with self.assertRaises(TypeError):
@@ -595,9 +595,9 @@ def test_shape(self):
d10 = Signal(max=1)
self.assertEqual(d10.shape(), (0, False))

def test_shape_bad(self):
def test_shape_wrong(self):
with self.assertRaises(TypeError,
msg="Width must be a non-negative integer, not '-10'"):
msg="Width must be a non-negative integer, not -10"):
Signal(-10)

def test_min_max_deprecated(self):
@@ -688,7 +688,7 @@ def test_domain(self):
self.assertEqual(s2.domain, "pix")

with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
msg="Clock domain name must be a string, not 1"):
ClockSignal(1)

def test_shape(self):
@@ -712,7 +712,7 @@ def test_domain(self):
self.assertEqual(s2.domain, "pix")

with self.assertRaises(TypeError,
msg="Clock domain name must be a string, not '1'"):
msg="Clock domain name must be a string, not 1"):
ResetSignal(1)

def test_shape(self):
4 changes: 2 additions & 2 deletions nmigen/test/test_hdl_dsl.py
Original file line number Diff line number Diff line change
@@ -625,10 +625,10 @@ def test_submodule_named_index(self):
def test_submodule_wrong(self):
m = Module()
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
m.submodules.foo = 1
with self.assertRaises(TypeError,
msg="Trying to add '1', which does not implement .elaborate(), as a submodule"):
msg="Trying to add 1, which does not implement .elaborate(), as a submodule"):
m.submodules += 1

def test_submodule_named_conflict(self):
4 changes: 2 additions & 2 deletions nmigen/test/test_hdl_ir.py
Original file line number Diff line number Diff line change
@@ -15,13 +15,13 @@ def elaborate(self, platform):
class FragmentGetTestCase(FHDLTestCase):
def test_get_wrong(self):
with self.assertRaises(AttributeError,
msg="Object 'None' cannot be elaborated"):
msg="Object None cannot be elaborated"):
Fragment.get(None, platform=None)

with self.assertWarns(UserWarning,
msg=".elaborate() returned None; missing return statement?"):
with self.assertRaises(AttributeError,
msg="Object 'None' cannot be elaborated"):
msg="Object None cannot be elaborated"):
Fragment.get(BadElaboratable(), platform=None)


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