-
Notifications
You must be signed in to change notification settings - Fork 58
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Output enable for Intel platform on multi I/O pins #297
Comments
@schwigi That looks like a bug to me,
Refer to ALTIOBUF IP COre User Guide, UG-01024 for details. |
I did some debugging runs and the problem is not in the platform.intel part. In lib/io.py:43 the oe width is hard coded to 1. For Intel FPGAs it is clear that you must use width here as well. Not sure however how other FPGAs behave though. |
No, the problem is in
This is deliberate: a wide tristate signal is treated as a single entity for the purposes of output enable. That is how (n)Migen define its behavior, which is completely independent of any platform. Any platform that has output enable with the same width as output should use If you want to control direction per-bit, you should instantiate a tristate per bit. |
@peteut: You are right, get_tristate should use |
Thanks for correcting my oversight ^.^' |
Not sure wether it is a bug or I have done something wrong.
I tried to get a 16 bit wide io pins, but the generated oe wire is only 1 bit. For the Intel altiobuf_bidir output enable signal must be as wide as the data lines.
Attached is a small python script to generate the output.
ioTest.py.zip
The text was updated successfully, but these errors were encountered: