Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: ccfbccc044e3
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 3f6abc0b7a12
Choose a head ref
  • 2 commits
  • 9 files changed
  • 1 contributor

Commits on Sep 8, 2019

  1. hdl.mem,lib,examples: use Signal.range().

    whitequark committed Sep 8, 2019
    Copy the full SHA
    eb04a25 View commit details
  2. hdl.dsl: add Default(), an alias for Case() with no arguments.

    Fixes #197.
    whitequark committed Sep 8, 2019
    Copy the full SHA
    3f6abc0 View commit details
Showing with 42 additions and 22 deletions.
  1. +1 −1 examples/basic/fsm.py
  2. +1 −1 examples/basic/por.py
  3. +4 −4 examples/basic/uart.py
  4. +3 −0 nmigen/hdl/dsl.py
  5. +2 −2 nmigen/hdl/mem.py
  6. +6 −6 nmigen/lib/coding.py
  7. +4 −4 nmigen/lib/fifo.py
  8. +18 −1 nmigen/test/test_hdl_dsl.py
  9. +3 −3 nmigen/test/test_lib_fifo.py
2 changes: 1 addition & 1 deletion examples/basic/fsm.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,7 @@ def __init__(self, divisor):
def elaborate(self, platform):
m = Module()

ctr = Signal(max=self.divisor)
ctr = Signal.range(self.divisor)
stb = Signal()
with m.If(ctr == 0):
m.d.sync += ctr.eq(self.divisor - 1)
2 changes: 1 addition & 1 deletion examples/basic/por.py
Original file line number Diff line number Diff line change
@@ -7,7 +7,7 @@
cd_sync = ClockDomain()
m.domains += cd_por, cd_sync

delay = Signal(max=255, reset=255)
delay = Signal.range(256, reset=255)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
m.d.comb += [
8 changes: 4 additions & 4 deletions examples/basic/uart.py
Original file line number Diff line number Diff line change
@@ -31,9 +31,9 @@ def __init__(self, divisor, data_bits=8):
def elaborate(self, platform):
m = Module()

tx_phase = Signal(max=self.divisor)
tx_phase = Signal.range(self.divisor)
tx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
tx_count = Signal(max=len(tx_shreg) + 1)
tx_count = Signal.range(len(tx_shreg) + 1)

m.d.comb += self.tx_o.eq(tx_shreg[0])
with m.If(tx_count == 0):
@@ -54,9 +54,9 @@ def elaborate(self, platform):
tx_phase.eq(self.divisor - 1),
]

rx_phase = Signal(max=self.divisor)
rx_phase = Signal.range(self.divisor)
rx_shreg = Signal(1 + self.data_bits + 1, reset=-1)
rx_count = Signal(max=len(rx_shreg) + 1)
rx_count = Signal.range(len(rx_shreg) + 1)

m.d.comb += self.rx_data.eq(rx_shreg[1:-1])
with m.If(rx_count == 0):
3 changes: 3 additions & 0 deletions nmigen/hdl/dsl.py
Original file line number Diff line number Diff line change
@@ -289,6 +289,9 @@ def Case(self, *values):
self._ctrl_context = "Switch"
self._statements = _outer_case

def Default(self):
return self.Case()

@contextmanager
def FSM(self, reset=None, domain="sync", name="fsm"):
self._check_context("FSM", context=None)
4 changes: 2 additions & 2 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,7 @@ def __init__(self, memory, domain, transparent):
self.domain = domain
self.transparent = transparent

self.addr = Signal(max=memory.depth,
self.addr = Signal.range(memory.depth,
name="{}_r_addr".format(memory.name), src_loc_at=2)
self.data = Signal(memory.width,
name="{}_r_data".format(memory.name), src_loc_at=2)
@@ -148,7 +148,7 @@ def __init__(self, memory, domain, priority, granularity):
self.priority = priority
self.granularity = granularity

self.addr = Signal(max=memory.depth,
self.addr = Signal.range(memory.depth,
name="{}_w_addr".format(memory.name), src_loc_at=2)
self.data = Signal(memory.width,
name="{}_w_data".format(memory.name), src_loc_at=2)
12 changes: 6 additions & 6 deletions nmigen/lib/coding.py
Original file line number Diff line number Diff line change
@@ -25,7 +25,7 @@ class Encoder(Elaboratable):
----------
i : Signal(width), in
One-hot input.
o : Signal(max=width), out
o : Signal.range(width), out
Encoded binary.
n : Signal, out
Invalid: either none or multiple input bits are asserted.
@@ -34,7 +34,7 @@ def __init__(self, width):
self.width = width

self.i = Signal(width)
self.o = Signal(max=max(2, width))
self.o = Signal.range(width)
self.n = Signal()

def elaborate(self, platform):
@@ -64,7 +64,7 @@ class PriorityEncoder(Elaboratable):
----------
i : Signal(width), in
Input requests.
o : Signal(max=width), out
o : Signal.range(width), out
Encoded binary.
n : Signal, out
Invalid: no input bits are asserted.
@@ -73,7 +73,7 @@ def __init__(self, width):
self.width = width

self.i = Signal(width)
self.o = Signal(max=max(2, width))
self.o = Signal.range(width)
self.n = Signal()

def elaborate(self, platform):
@@ -98,7 +98,7 @@ class Decoder(Elaboratable):
Attributes
----------
i : Signal(max=width), in
i : Signal.range(width), in
Input binary.
o : Signal(width), out
Decoded one-hot.
@@ -108,7 +108,7 @@ class Decoder(Elaboratable):
def __init__(self, width):
self.width = width

self.i = Signal(max=max(2, width))
self.i = Signal.range(width)
self.n = Signal()
self.o = Signal(width)

8 changes: 4 additions & 4 deletions nmigen/lib/fifo.py
Original file line number Diff line number Diff line change
@@ -136,7 +136,7 @@ class SyncFIFO(Elaboratable, FIFOInterface):
def __init__(self, width, depth, fwft=True):
super().__init__(width, depth, fwft)

self.level = Signal(max=depth + 1)
self.level = Signal.range(depth + 1)
self.replace = Signal()

def elaborate(self, platform):
@@ -153,8 +153,8 @@ def elaborate(self, platform):
wrport = m.submodules.wrport = storage.write_port()
rdport = m.submodules.rdport = storage.read_port(
domain="comb" if self.fwft else "sync", transparent=self.fwft)
produce = Signal(max=self.depth)
consume = Signal(max=self.depth)
produce = Signal.range(self.depth)
consume = Signal.range(self.depth)

m.d.comb += [
wrport.addr.eq(produce),
@@ -234,7 +234,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
def __init__(self, width, depth):
super().__init__(width, depth, fwft=True)

self.level = Signal(max=depth + 1)
self.level = Signal.range(depth + 1)

def elaborate(self, platform):
m = Module()
19 changes: 18 additions & 1 deletion nmigen/test/test_hdl_dsl.py
Original file line number Diff line number Diff line change
@@ -307,7 +307,7 @@ def test_Switch(self):
)
""")

def test_Switch_default(self):
def test_Switch_default_Case(self):
m = Module()
with m.Switch(self.w1):
with m.Case(3):
@@ -324,6 +324,23 @@ def test_Switch_default(self):
)
""")

def test_Switch_default_Default(self):
m = Module()
with m.Switch(self.w1):
with m.Case(3):
m.d.comb += self.c1.eq(1)
with m.Default():
m.d.comb += self.c2.eq(1)
m._flush()
self.assertRepr(m._statements, """
(
(switch (sig w1)
(case 0011 (eq (sig c1) (const 1'd1)))
(default (eq (sig c2) (const 1'd1)))
)
)
""")

def test_Switch_const_test(self):
m = Module()
with m.Switch(1):
6 changes: 3 additions & 3 deletions nmigen/test/test_lib_fifo.py
Original file line number Diff line number Diff line change
@@ -52,7 +52,7 @@ def __init__(self, width, depth, fwft, rdomain, wdomain):
self.wdomain = wdomain

self.replace = Signal()
self.level = Signal(max=self.depth + 1)
self.level = Signal.range(self.depth + 1)

def elaborate(self, platform):
m = Module()
@@ -61,8 +61,8 @@ def elaborate(self, platform):
wrport = m.submodules.wrport = storage.write_port(domain=self.wdomain)
rdport = m.submodules.rdport = storage.read_port (domain="comb")

produce = Signal(max=self.depth)
consume = Signal(max=self.depth)
produce = Signal.range(self.depth)
consume = Signal.range(self.depth)

m.d.comb += self.readable.eq(self.level > 0)
m.d.comb += rdport.addr.eq((consume + 1) % self.depth)