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base repository: m-labs/nmigen-boards
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head repository: m-labs/nmigen-boards
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compare: b50e52c03734
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Oct 3, 2019

  1. Factor out "sdram" resource.

    whitequark committed Oct 3, 2019
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    07156e6 View commit details
  2. Factor out "nor_flash" resource.

    whitequark committed Oct 3, 2019
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    b50e52c View commit details
Showing with 62 additions and 1 deletion.
  1. +62 −1 nmigen_boards/resources/memory.py
63 changes: 62 additions & 1 deletion nmigen_boards/resources/memory.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,10 @@
from nmigen.build import *


__all__ = ["SPIFlashResources", "SDCardResources", "SRAMResource"]
__all__ = [
"SPIFlashResources", "SDCardResources",
"SRAMResource", "SDRAMResource", "NORFlashResources",
]


def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
@@ -94,3 +97,61 @@ def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sram", ios=io)


def SDRAMResource(*args, clk, cke=None, cs, we, ras, cas, ba, a, dq, dqm, attrs=None):
io = []
io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
if cke is not None:
io.append(Subsignal("clk_en", Pins(cke, dir="o", assert_width=1)))
io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io.append(Subsignal("ras", PinsN(ras, dir="o", assert_width=1)))
io.append(Subsignal("cas", PinsN(cas, dir="o", assert_width=1)))
io.append(Subsignal("ba", Pins(ba, dir="o")))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("dq", Pins(dq, dir="io")))
if dqm is not None:
io.append(Subsignal("dqm", Pins(dqm, dir="o")))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sdram", ios=io)


def NORFlashResources(*args, rst=None, byte=None, cs, oe, we, wp, by, a, dq, attrs=None):
resources = []

io_common = []
if rst is not None:
io_common.append(Subsignal("rst", Pins(rst, dir="o", assert_width=1)))
io_common.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
io_common.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
io_common.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io_common.append(Subsignal("wp", PinsN(wp, dir="o", assert_width=1)))
io_common.append(Subsignal("rdy", Pins(by, dir="i", assert_width=1)))

if byte is None:
io_8bit = list(io_common)
io_8bit.append(Subsignal("a", Pins(a, dir="o")))
io_8bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=8)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
name_suffix="8bit"))
else:
*dq_0_14, dq15_am1 = dq.split()

# If present in a requested resource, this pin needs to be strapped correctly.
io_common.append(Subsignal("byte", PinsN(byte, dir="o", assert_width=1)))

io_8bit = list(io_common)
io_8bit.append(Subsignal("a", Pins(" ".join((dq15_am1, a)), dir="o")))
io_8bit.append(Subsignal("dq", Pins(" ".join(dq_0_14[:8]), dir="io", assert_width=8)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_8bit,
name_suffix="8bit"))

io_16bit = list(io_common)
io_16bit.append(Subsignal("a", Pins(a, dir="o")))
io_16bit.append(Subsignal("dq", Pins(dq, dir="io", assert_width=16)))
resources.append(Resource.family(*args, default_name="nor_flash", ios=io_16bit,
name_suffix="16bit"))

return resources