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base repository: m-labs/nmigen-boards
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  • 3 commits
  • 26 files changed
  • 1 contributor

Commits on Oct 3, 2019

  1. Factor out "sd_card_{1bit,4bit,spi}" resources.

    whitequark committed Oct 3, 2019
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    b033d53 View commit details
  2. Reorganize resource taxonomy.

    The current hierarchy isn't particularly well suited to resources
    like SDRAM or NOR flash, so make it much less fine-grained but easier
    to use and less nitpicky.
    whitequark committed Oct 3, 2019
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    c7c6370 View commit details
  3. [breaking-change] Fix polarity of "dm" signal in "memory" resource.

    LB# and UB# enable writing their corresponding byte. The "m" in "dm"
    means mask; that is, logical high masks (prevents) the byte from
    being written. This means that it should use Pins(), not PinsN(),
    to get the behavior implied by "mask".
    whitequark committed Oct 3, 2019
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    50acf4a View commit details
2 changes: 1 addition & 1 deletion nmigen_boards/arty_a7.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_7series import *
from .dev import *
from .resources import *


__all__ = ["ArtyA7Platform"]
2 changes: 1 addition & 1 deletion nmigen_boards/atlys.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_spartan_3_6 import *
from .dev import *
from .resources import *


__all__ = ["AtlysPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/blackice.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["BlackIcePlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/blackice_ii.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["BlackIceIIPlatform"]
5 changes: 0 additions & 5 deletions nmigen_boards/dev/__init__.py

This file was deleted.

38 changes: 0 additions & 38 deletions nmigen_boards/dev/flash.py

This file was deleted.

33 changes: 0 additions & 33 deletions nmigen_boards/dev/spi.py

This file was deleted.

20 changes: 0 additions & 20 deletions nmigen_boards/dev/sram.py

This file was deleted.

File renamed without changes.
File renamed without changes.
2 changes: 1 addition & 1 deletion nmigen_boards/fomu_hacker.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["FomuHackerPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/ice40_hx1k_blink_evn.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["ICE40HX1KBlinkEVNPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/ice40_hx8k_b_evn.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["ICE40HX8KBEVNPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/icebreaker.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["ICEBreakerPlatform"]
3 changes: 1 addition & 2 deletions nmigen_boards/icestick.py
Original file line number Diff line number Diff line change
@@ -3,8 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .dev.uart import IrDAResource
from .resources import *


__all__ = ["ICEStickPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/kc705.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_7series import *
from .dev import *
from .resources import *


__all__ = ["KC705Platform"]
3 changes: 1 addition & 2 deletions nmigen_boards/mercury.py
Original file line number Diff line number Diff line change
@@ -3,8 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_spartan_3_6 import *
from .dev import *
from .dev.display import Display7SegResource
from .resources import *


__all__ = ["MercuryPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/numato_mimas.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_spartan_3_6 import *
from .dev import *
from .resources import *


__all__ = ["NumatoMimasPlatform"]
4 changes: 4 additions & 0 deletions nmigen_boards/resources/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
from .display import *
from .interface import *
from .memory import *
from .user import *
File renamed without changes.
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from nmigen.build import *


__all__ = ["UARTResource", "IrDAResource"]
__all__ = ["UARTResource", "IrDAResource", "SPIResource"]


def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
@@ -30,6 +30,7 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
# Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
# be specified, and it is mapped to a logic level en subsignal.
assert (en is not None) ^ (sd is not None)

io = []
io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
@@ -40,3 +41,32 @@ def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
if attrs is not None:
io.append(attrs)
return Resource("irda", number, *io)


def SPIResource(*args, cs, clk, mosi, miso, int=None, reset=None, attrs=None, role="host"):
assert role in ("host", "device")

io = []
if role == "host":
io.append(Subsignal("cs", PinsN(cs, dir="o")))
io.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
else: # device
io.append(Subsignal("cs", PinsN(cs, dir="i", assert_width=1)))
io.append(Subsignal("clk", Pins(clk, dir="i", assert_width=1)))
io.append(Subsignal("mosi", Pins(mosi, dir="i", assert_width=1)))
io.append(Subsignal("miso", Pins(miso, dir="oe", assert_width=1)))
if int is not None:
if role == "host":
io.append(Subsignal("int", Pins(int, dir="i")))
else:
io.append(Subsignal("int", Pins(int, dir="oe", assert_width=1)))
if reset is not None:
if role == "host":
io.append(Subsignal("reset", Pins(reset, dir="o")))
else:
io.append(Subsignal("reset", Pins(reset, dir="i", assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="spi", ios=io)
96 changes: 96 additions & 0 deletions nmigen_boards/resources/memory.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,96 @@
from nmigen.build import *


__all__ = ["SPIFlashResources", "SDCardResources", "SRAMResource"]


def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None, attrs=None):
resources = []

io_all = []
if attrs is not None:
io_all.append(attrs)
io_all.append(Subsignal("cs", PinsN(cs, dir="o")))
io_all.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))

io_1x = list(io_all)
io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", assert_width=1)))
io_1x.append(Subsignal("miso", Pins(miso, dir="i", assert_width=1)))
if wp is not None and hold is not None:
io_1x.append(Subsignal("wp", PinsN(wp, dir="o", assert_width=1)))
io_1x.append(Subsignal("hold", PinsN(hold, dir="o", assert_width=1)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_1x,
name_suffix="1x"))

io_2x = list(io_all)
io_2x.append(Subsignal("dq", Pins(" ".join([mosi, miso]), dir="io",
assert_width=2)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_2x,
name_suffix="2x"))

if wp is not None and hold is not None:
io_4x = list(io_all)
io_4x.append(Subsignal("dq", Pins(" ".join([mosi, miso, wp, hold]), dir="io",
assert_width=4)))
resources.append(Resource.family(*args, default_name="spi_flash", ios=io_4x,
name_suffix="4x"))

return resources


def SDCardResources(*args, clk, cmd, dat0, dat1=None, dat2=None, dat3=None,
cd=None, wp=None, attrs=None):
resources = []

io_common = []
if attrs is not None:
io_common.append(attrs)
if cd is not None:
io_common.append(Subsignal("cd", Pins(cd, dir="i", assert_width=1)))
if wp is not None:
io_common.append(Subsignal("wp", PinsN(wp, dir="i", assert_width=1)))

io_native = list(io_common)
io_native.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io_native.append(Subsignal("cmd", Pins(cmd, dir="o", assert_width=1)))

io_1bit = list(io_native)
io_1bit.append(Subsignal("dat", Pins(dat0, dir="io", assert_width=1)))
if dat3 is not None: # works as electronic card detect
io_1bit.append(Subsignal("ecd", Pins(dat3, dir="i", assert_width=1)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_1bit,
name_suffix="1bit"))

if dat1 is not None and dat2 is not None and dat3 is not None:
io_4bit = list(io_native)
io_4bit.append(Subsignal("dat", Pins(" ".join((dat0, dat1, dat2, dat3)), dir="io",
assert_width=4)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_4bit,
name_suffix="4bit"))

if dat3 is not None:
io_spi = list(io_common)
io_spi.append(Subsignal("cs", PinsN(dat3, dir="io"))) # doubles as electronic card detect
io_spi.append(Subsignal("clk", Pins(clk, dir="o", assert_width=1)))
io_spi.append(Subsignal("mosi", Pins(cmd, dir="o", assert_width=1)))
io_spi.append(Subsignal("miso", Pins(dat0, dir="i", assert_width=1)))
resources.append(Resource.family(*args, default_name="sd_card", ios=io_spi,
name_suffix="spi"))

return resources


def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
io = []
io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
if oe is not None:
# Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
io.append(Subsignal("a", Pins(a, dir="o")))
io.append(Subsignal("d", Pins(d, dir="io")))
if dm is not None:
io.append(Subsignal("dm", Pins(dm, dir="o"))) # dm="LB# UB#"
if attrs is not None:
io.append(attrs)
return Resource.family(*args, default_name="sram", ios=io)
File renamed without changes.
2 changes: 1 addition & 1 deletion nmigen_boards/sk_xc6slx9.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.xilinx_spartan_3_6 import *
from .dev import *
from .resources import *


__all__ = ["SK_XC6SLX9Platform"]
2 changes: 1 addition & 1 deletion nmigen_boards/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ice40 import *
from .dev import *
from .resources import *


__all__ = ["TinyFPGABXPlatform"]
2 changes: 1 addition & 1 deletion nmigen_boards/versa_ecp5.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

from nmigen.build import *
from nmigen.vendor.lattice_ecp5 import *
from .dev import *
from .resources import *


__all__ = ["VersaECP5Platform"]