Add Terasic DE0-CV #31
Conversation
| Resource("clk50", 2, Pins("E10", dir="i"), | ||
| Clock(50e6), Attrs(io_standard="3.3-V LVTTL")), | ||
| Resource("clk50", 3, Pins("V15", dir="i"), | ||
| Clock(50e6), Attrs(io_standard="3.3-V LVTTL")), |
There was a problem hiding this comment.
Wasn't there some sort of global reset pin?
There was a problem hiding this comment.
P22 (DEV_CLRN) is connected to a button to reset the FPGA. To me it doesn't make much sense to add that as a device when the world ends if it's pressed.
There was a problem hiding this comment.
Is that pin hardcoded in the toolchain? Or is it actually usable in user designs?
There was a problem hiding this comment.
According to the pinout list it's fixed as DEV_CLRn, so I would imagine it's not usable in designs.
There was a problem hiding this comment.
I think it's usable in user designs:
You can also tie the DEV_CLRn pin to VCCIO or leave the DEV_CLRn pin unconnected provided that the Enable device-wide reset (DEV_CLRn) option is disabled and not used as a user I/O pin
There was a problem hiding this comment.
ECP5 has a similar "fixed function" pin which is actually totally arbitrary and just routed like any other global input.
But I think this doesn't really matter, I'll merge as it is since it looks fine.
No description provided.