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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 964c67453fc8
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Oct 4, 2019

  1. back.rtlil: avoid unsoundness for division by zero.

    Fixes #238.
    whitequark committed Oct 4, 2019
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    964c674 View commit details
Showing with 12 additions and 0 deletions.
  1. +12 −0 nmigen/back/rtlil.py
12 changes: 12 additions & 0 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -505,6 +505,18 @@ def on_Operator_binary(self, value):
"B_WIDTH": rhs_bits,
"Y_WIDTH": res_bits,
}, src=src(value.src_loc))
if value.op in ("//", "%"):
# RTLIL leaves division by zero undefined, but we require it to return zero.
divmod_res = res
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
self.s.rtlil.cell("$mux", ports={
"\\A": divmod_res,
"\\B": self(ast.Const(0, (res_bits, res_sign))),
"\\S": self(lhs == 0),
"\\Y": res,
}, params={
"WIDTH": res_bits
}, src=src(value.src_loc))
return res

def on_Operator_mux(self, value):