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Branch: revert_clock_propigation #315

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litghost opened this issue Nov 6, 2019 · 1 comment
Closed
4 tasks

Branch: revert_clock_propigation #315

litghost opened this issue Nov 6, 2019 · 1 comment
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wip Work in Progress branch that needs work to be deleted/sent upstream
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Merge changes upstream

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@litghost
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litghost commented Nov 6, 2019

Why did we need this? (what does this change enable us to do)

verilog-to-routing#1038 caused a regression in VPR that prevents PLL's to function.

What did it change?

It reverts clock propigation through block box

Should it be merged upstream - if not, when can we delete it?

No, this should not be merged upstream. Instead the feature that it reverts, should be fixed.

What is needed to get this merged / deleted?

  • is the implementation work to make suitable for merging / deletion completed?
  • Is there an associated test?
  • is this currently part of the Conda package?
  • is this properly cleaned up in our local repositories?

Tracker / branch / PR & other useful links

Upstream issue: verilog-to-routing#1038
Upstream PR showing failure: verilog-to-routing#1041
@acomodi acomodi added the wip Work in Progress branch that needs work to be deleted/sent upstream label Nov 26, 2019
@acomodi acomodi added this to Not for merging upstream in Merge changes upstream Nov 28, 2019
@acomodi acomodi moved this from Not for merging upstream to In Conda Package - Pending other cleanup in Merge changes upstream Apr 14, 2020
@acomodi
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acomodi commented Apr 30, 2020

This is in conda and already integrated in archdefs. Closing

@acomodi acomodi closed this as completed Apr 30, 2020
Merge changes upstream automation moved this from In Conda Package - Pending other cleanup to Completed (merged upstream & used locally) Apr 30, 2020
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