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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 9749c70730f7
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Nov 7, 2019

  1. hdl.ir: lower domains before resolving hierarchy conflicts.

    Otherwise, two subfragments with the same local clock domain would
    not be able to drive its clock or reset signals. This can be easily
    hit if using two ResetSynchronizers in one module.
    
    Fixes #265.
    whitequark committed Nov 7, 2019
    Copy the full SHA
    9749c70 View commit details
Showing with 15 additions and 1 deletion.
  1. +1 −1 nmigen/hdl/ir.py
  2. +14 −0 nmigen/test/test_hdl_ir.py
2 changes: 1 addition & 1 deletion nmigen/hdl/ir.py
Original file line number Diff line number Diff line change
@@ -540,8 +540,8 @@ def prepare(self, ports=None, missing_domain=lambda name: ClockDomain(name)):

fragment = SampleLowerer()(self)
new_domains = fragment._propagate_domains(missing_domain)
fragment._resolve_hierarchy_conflicts()
fragment = DomainLowerer()(fragment)
fragment._resolve_hierarchy_conflicts()
if ports is None:
fragment._propagate_ports(ports=(), all_undef_as_ports=True)
else:
14 changes: 14 additions & 0 deletions nmigen/test/test_hdl_ir.py
Original file line number Diff line number Diff line change
@@ -642,6 +642,20 @@ def test_explicit_flatten(self):
self.f1._resolve_hierarchy_conflicts(mode="silent")
self.assertEqual(self.f1.subfragments, [])

def test_no_conflict_local_domains(self):
f1 = Fragment()
cd1 = ClockDomain("d", local=True)
f1.add_domains(cd1)
f1.add_driver(ClockSignal("d"))
f2 = Fragment()
cd2 = ClockDomain("d", local=True)
f2.add_domains(cd2)
f2.add_driver(ClockSignal("d"))
f3 = Fragment()
f3.add_subfragment(f1)
f3.add_subfragment(f2)
f3.prepare()


class InstanceTestCase(FHDLTestCase):
def test_construct(self):