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Branch: fix_cache_of_timing_info #313

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1 of 4 tasks

litghost opened this issue Nov 5, 2019 · 1 comment

litghost commented Nov 5, 2019

Why did we need this? (what does this change enable us to do)

Fixes router iteration display, which was showing stale data, see verilog-to-routing#1036

What did it change?

Should it be merged upstream - if not, when can we delete it?

PR already opened upstream.

What is needed to get this merged / deleted?

is the implementation work to make suitable for merging / deletion completed?
Is there an associated test?
is this currently part of the Conda package?
is this properly cleaned up in our local repositories?

Tracker / branch / PR & other useful links

verilog-to-routing#1036
verilog-to-routing#1037

Author

litghost commented Nov 6, 2019

Merged upstream

litghost closed this as completed

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