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Probably should just restrict them to unsigned values only, at least until someone implements correct behavior for signed values on top of Yosys' semantics (which is not trivial and not clearly desirable).
Incorrect: because Python uses div/mod semantics, and Verilog (and thus Yosys) uses quo/rem semantics.
Unsound: because nMigen should return 0 for
x//0
andx%0
, but Verilog (and thus Yosys) returns'x
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