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Division and modulo are incorrect and unsound #238

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whitequark opened this issue Sep 28, 2019 · 1 comment
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Division and modulo are incorrect and unsound #238

whitequark opened this issue Sep 28, 2019 · 1 comment
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@whitequark
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Incorrect: because Python uses div/mod semantics, and Verilog (and thus Yosys) uses quo/rem semantics.

Unsound: because nMigen should return 0 for x//0 and x%0, but Verilog (and thus Yosys) returns 'x.
@whitequark whitequark added the bug label Sep 28, 2019
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Probably should just restrict them to unsigned values only, at least until someone implements correct behavior for signed values on top of Yosys' semantics (which is not trivial and not clearly desirable).

@whitequark whitequark added this to the 0.1 milestone Sep 28, 2019
whitequark added a commit that referenced this issue Oct 4, 2019
hdl.ast: prohibit signed divisors.
de34728 
See #238.
whitequark added a commit that referenced this issue Oct 4, 2019
back.rtlil: avoid unsoundness for division by zero.
964c674 
Fixes #238.
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