from nmigen import *
from nmigen.cli import main
from nmigen.asserts import *


class TestCase(Elaboratable):
    def __init__(self):
        self.input = Signal(8)
        self.output = Signal()

    def elaborate(self, platform):
        m = Module()

        with m.If(self.input.matches(7)):
            m.d.comb += self.output.eq(1)
        with m.Elif(self.input.matches("1---0000")):
            m.d.comb += self.output.eq(1)
        with m.Else():
            m.d.comb += self.output.eq(0)
        return m


if __name__ == "__main__":
    clk = Signal()
    rst = Signal()

    pos = ClockDomain()
    pos.clk = clk
    pos.rst = rst

    testcase = TestCase()

    m = Module()
    m.domains.pos = pos
    m.submodules.testcase = testcase

    main(
        m,
        ports=[clk, rst, testcase.input, testcase.output],
        platform="formal")

attribute \generator "nMigen"
attribute \nmigen.hierarchy "top.testcase"
module \testcase
  attribute \src "test_case.py:8"
  wire width 8 input 0 \input
  attribute \src "test_case.py:9"
  wire width 1 output 1 \output
  attribute \src "test_case.py:14"
  wire width 1 $1
  attribute \src "test_case.py:14"
  cell $eq $2
    parameter \A_SIGNED 0
    parameter \A_WIDTH 8
    parameter \B_SIGNED 0
    parameter \B_WIDTH 3
    parameter \Y_WIDTH 1
    connect \A \input
    connect \B 3'111
    connect \Y $1
  end
  attribute \src "test_case.py:16"
  wire width 8 $3
  attribute \src "test_case.py:16"
  cell $and $4
    parameter \A_SIGNED 0
    parameter \A_WIDTH 8
    parameter \B_SIGNED 0
    parameter \B_WIDTH 8
    parameter \Y_WIDTH 8
    connect \A \input
    connect \B 8'10001111
    connect \Y $3
  end
  attribute \src "test_case.py:16"
  wire width 1 $5
  attribute \src "test_case.py:16"
  cell $eq $6
    parameter \A_SIGNED 0
    parameter \A_WIDTH 8
    parameter \B_SIGNED 0
    parameter \B_WIDTH 8
    parameter \Y_WIDTH 1
    connect \A $3
    connect \B 8'10000000
    connect \Y $5
  end
  process $group_0
    assign \output 1'0
    attribute \src "test_case.py:14"
    switch { $5 $1 }
      attribute \src "test_case.py:14"
      case 2'-1
        assign \output 1'1
      attribute \src "test_case.py:16"
      case 2'1-
        assign \output 1'1
      attribute \src "test_case.py:18"
      case
        assign \output 1'0
    end
    sync init
  end
end
attribute \generator "nMigen"
attribute \top 1
attribute \nmigen.hierarchy "top"
module \top
  attribute \src "test_case.py:24"
  wire width 1 input 0 \clk
  attribute \src "test_case.py:25"
  wire width 1 input 1 \rst
  attribute \src "test_case.py:8"
  wire width 8 input 2 \input
  attribute \src "test_case.py:9"
  wire width 1 output 3 \output
  cell \testcase \testcase
    connect \input \input
    connect \output \output
  end
end

/* Generated by Yosys 0.9+36 (git sha1 4aa505d1, clang 6.0.0-1ubuntu2 -fPIC -Os) */

(* \nmigen.hierarchy  = "top.testcase" *)
(* generator = "nMigen" *)
module testcase(\output , \input );
  (* src = "test_case.py:14" *)
  wire \$1 ;
  (* src = "test_case.py:16" *)
  wire [7:0] \$3 ;
  (* src = "test_case.py:16" *)
  wire \$5 ;
  (* src = "test_case.py:8" *)
  input [7:0] \input ;
  (* src = "test_case.py:9" *)
  output \output ;
  reg \output ;
  assign \$1  = \input  == (* src = "test_case.py:14" *) 3'h7;
  assign \$3  = \input  & (* src = "test_case.py:16" *) 8'h8f;
  assign \$5  = \$3  == (* src = "test_case.py:16" *) 8'h80;
  always @* begin
    (* src = "test_case.py:14" *)
    casez ({ \$5 , \$1  })
      /* src = "test_case.py:14" */
      2'b?1:
          \output  = 1'h1;
      /* src = "test_case.py:16" */
      2'b1?:
          \output  = 1'h1;
      /* src = "test_case.py:18" */
      default:
          \output  = 1'h0;
    endcase
  end
endmodule

(* \nmigen.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "nMigen" *)
module top(rst, \input , \output , clk);
  (* src = "test_case.py:24" *)
  input clk;
  (* src = "test_case.py:8" *)
  input [7:0] \input ;
  (* src = "test_case.py:9" *)
  output \output ;
  (* src = "test_case.py:25" *)
  input rst;
  testcase testcase (
    .\input (\input ),
    .\output (\output )
  );
endmodule