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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 42805ad95974
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Sep 12, 2019

  1. hdl.mem: use keyword-only arguments as appropriate.

    whitequark committed Sep 12, 2019
    Copy the full SHA
    42805ad View commit details
Showing with 8 additions and 8 deletions.
  1. +8 −8 nmigen/hdl/mem.py
16 changes: 8 additions & 8 deletions nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@


class Memory:
def __init__(self, width, depth, init=None, name=None, simulate=True):
def __init__(self, width, depth, *, init=None, name=None, simulate=True):
if not isinstance(width, int) or width < 0:
raise TypeError("Memory width must be a non-negative integer, not '{!r}'"
.format(width))
@@ -53,12 +53,12 @@ def init(self, new_init):
raise TypeError("Memory initialization value at address {:x}: {}"
.format(addr, e)) from None

def read_port(self, domain="sync", transparent=True):
def read_port(self, domain="sync", *, transparent=True):
if domain == "comb" and not transparent:
raise ValueError("Read port cannot be simultaneously asynchronous and non-transparent")
return ReadPort(self, domain, transparent)
return ReadPort(self, domain, transparent=transparent)

def write_port(self, domain="sync", priority=0, granularity=None):
def write_port(self, domain="sync", *, priority=0, granularity=None):
if granularity is None:
granularity = self.width
if not isinstance(granularity, int) or granularity < 0:
@@ -70,15 +70,15 @@ def write_port(self, domain="sync", priority=0, granularity=None):
.format(granularity, self.width))
if self.width // granularity * granularity != self.width:
raise ValueError("Write port granularity must divide memory width evenly")
return WritePort(self, domain, priority, granularity)
return WritePort(self, domain, priority=priority, granularity=granularity)

def __getitem__(self, index):
"""Simulation only."""
return self._array[index]


class ReadPort(Elaboratable):
def __init__(self, memory, domain, transparent):
def __init__(self, memory, domain, *, transparent):
self.memory = memory
self.domain = domain
self.transparent = transparent
@@ -142,7 +142,7 @@ def elaborate(self, platform):


class WritePort(Elaboratable):
def __init__(self, memory, domain, priority, granularity):
def __init__(self, memory, domain, *, priority, granularity):
self.memory = memory
self.domain = domain
self.priority = priority
@@ -189,7 +189,7 @@ class DummyPort:
It does not include any read/write port specific attributes, i.e. none besides ``"domain"``;
any such attributes may be set manually.
"""
def __init__(self, width, addr_bits, domain="sync", name=None, granularity=None):
def __init__(self, width, addr_bits, domain="sync", *, name=None, granularity=None):
self.domain = domain

if granularity is None: