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Consider being able to access FSM next #205
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oMigen had a feature similar to this and it was extremely prone to combinatorial loops, so I never ported it to nMigen. This feature request sounds a bit like an XY problem. Can you give more details about your code? Hopefully there is a more elegant way to solve it (or maybe not, and the motivation would be stronger then). |
I think that if you can't read |
Still a WIP, but here's a bit from the instruction sequencer module, whose purpose is, among other things, to tell the machine cycler module what machine cycle to perform after the current machine cycle is done (machine cycles consist of 3 or more clock cycles):
So if, during execution of an instruction, the instruction needs to read memory, it can call The alternate way would be to not have to define that function, and instead just set
In my particular case I think the function approach probably is more readable, but maybe there's a use case for reading |
Here's another example. Suppose I had an FSM with, say, 30 states. And I'd like to do some combinatorial assignment on 20 of the states, and something different on 10 of the states. I could do this:
or, I could do this:
I think the latter is more readable, since it groups all the logic associated with those assignments together, rather than having it scattered throughout the FSM. |
Why shouldn't the last example work more like:
|
I think it's kind of non-obvious that nmigen lets you do this Duff's-devicey stuff with cases, as opposed to being more structured like they are in languages like C#. |
Right now it doesn't (#195) and well, maybe it shouldn't. Good question. |
er, right; I was mixing up |
Note that |
oh, okay. Apparently I just don't understand nmigen. |
Closing in favor of more general discussion in #206. |
I've hit a case in my Z80 processor where I have a module with an FSM. Based on that FSM's
next
, I'd like to assign some signals for some other modules. As an example, the sequencer module that contains the FSM might set the FSM'snext
to"INITIATE_READ"
. This should cause the machine cycler module to begin a memory read cycle.Currently, the only way to do that seems to be to ensure that everywhere I do
m.next = "INITIATE_READ"
I also do something likeself.next_cycle.eq(MCycle.MEMRD)
. This is clearly error-prone. I could just abstract that into a method and call it something likeinitiate_read()
. But how about the ability to just set up am.d.comb
that assignsself.next_cycle
based onfsm.next
?The text was updated successfully, but these errors were encountered: