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Support constraints on interior signals in nextpnr #88

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whitequark opened this issue Jun 5, 2019 · 3 comments
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Support constraints on interior signals in nextpnr #88

whitequark opened this issue Jun 5, 2019 · 3 comments
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improvement toolchain:nextpnr
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0.1

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@whitequark
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This is technically a bug in all cases, but it is not actually visible in most circumstances, as the signals that appear in constraint files are always ports, ports are assigned names first, and port names are never duplicates when returned by the platform layer. However, it would break most attempts to add interior frequency constraints, like for PLL output.

A complication is that it is currently not possible to reliably add constraints on interior signals in nextpnr (and even ports became reliable only after #71).
@whitequark whitequark added the bug label Jun 5, 2019
@Wren6991 Wren6991 mentioned this issue Jun 28, 2019
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@dlharmon dlharmon mentioned this issue Sep 9, 2019
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whitequark added a commit that referenced this issue Sep 11, 2019
build.plat,vendor: allow clock constraints on arbitrary signals.
8c30147 
Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
@whitequark
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Since 8c30147, constraints on interior signals are supported if the toolchain supports them.

@whitequark whitequark changed the title Signal names are not translated for constraints, etc. Support constraints on interior signals in nextpnr Sep 11, 2019
@whitequark
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whitequark commented Sep 14, 2019 •
edited

This should be fixed in YosysHQ/nextpnr#329, but needs some adjustments to vendor code.

@whitequark whitequark added this to the 0.1 milestone Sep 20, 2019
@whitequark
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cc @dlharmon

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