from nmigen import *
from nmigen.back import verilog, rtlil

class Good(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        s = Signal(reset=1)
        m.submodules.ins = ins = Instance("GOOD",
            i_in=s,
            o_out=s,
        )
        return m

class Bad(Elaboratable):
    def elaborate(self, platform):
        m = Module()
        s = Signal(reset=1)
        m.submodules.ins = ins = Instance("BAD",
            o_out=s,
            i_in=s,
        )
        return m

def main():
    print(rtlil.convert(Bad(), name="bad"))
    print(rtlil.convert(Good(), name="good"))

if __name__ == "__main__":
    main()